Renesas SH7616, Руководство по оборудованию

Страница: 253 / 935

Section 6 User Break Controller (UBC)
Rev. 2.00 Mar 09, 2006 page 227 of 906
REJ09B0292-0200
6.2.19 Break Control Register (BRCR)
BRCRH
Bit: 31 30 29 28 27 26 25 24
CMFCA CMFPA — — PCTE PCBA — —
Initial value: 0 0 0 0 0 0 0 0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 23 22 21 20 19 18 17 16
CMFCB CMFPB — SEQ1 SEQ0 PCBB — —
Initial value: 0 0 0 0 0 0 0 0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
BRCRL
Bit: 15 14 13 12 11 10 9 8
CMFCC CMFPC ETBEC — DBEC PCBC — —
Initial value: 0 0 0 0 0 0 0 0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 7 6 5 4 3 2 1 0
CMFCD CMFPD ETBED — DBED PCBD — —
Initial value: 0 0 0 0 0 0 0 0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
The break control register (BRCR) is used to make the following settings:
1. Setting of independent channel mode or sequential condition mode for channels A, B, C, and D
2. Selection of pre- or post-instruction-execution break in case of an instruction fetch cycle
3. Selection of whether the data bus is to be included in the comparison conditions for channels C
and D
4. Selection of whether an execution-times break is to be set for channels C and D
5. Selection of whether a PC trace is to be executed
BRCR also contains flags that are set when a condition is satisfied. BRCR is initialized to
H'00000000 by a power-on reset; after a manual reset, its value is undefined.