Renesas SH7616, Руководство по оборудованию

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Section 8 Cache
Rev. 2.00 Mar 09, 2006 page 362 of 906
REJ09B0292-0200
When a cache miss occurs, the way for replacement is determined using the LRU information, and
the read address from the CPU is written in the address array for that way. Simultaneously, the
valid bit is set to 1. Since the 16 bytes of data for replacing the data array are simultaneously read,
the address on the cache address bus is output to the internal address bus and 4 longwords are read
consecutively. The access order is such that, for the address output to the internal address, the byte
address within the line is sequentially incremented by 4, so that the longword that contains the
address to be read from the cache comes last. The read data on the internal data bus is written
sequentially to the cache data array. One cycle after the last data is written to the cache data array,
it is also output to the cache data bus and the read data is sent to the CPU.
The internal address bus and internal data bus also function as pipelines, just like the cache bus
(figure 8.4).
Address A
MA
EX
EX WB
MA
Data array write
Address B
Address A
+12
Address A
Address A
+8
Address A
+4
Address A
+4
Address A
+8
Address A
+12
Address A
Cache tag comparison
CPU
pipeline
stage
I
φ
Cache
address
bus
Cache
data bus
Internal
address
bus
Internal
data bus
EX: Instruction execution
MA: Memory access
WB: Write-back
Address A
Figure 8.4 Read Access in Case of a Cache Miss