Renesas SH7616, Руководство по оборудованию

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Section 6 User Break Controller (UBC)
Rev. 2.00 Mar 09, 2006 page 207 of 906
REJ09B0292-0200
6.2.4 Break Address Register B (BARB)
BARBH
Bit: 15 14 13 12 11 10 9 8
BAB31 BAB30 BAB29 BAB28 BAB27 BAB26 BAB25 BAB24
Initial value: 0 0 0 0 0 0 0 0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 7 6 5 4 3 2 1 0
BAB23 BAB22 BAB21 BAB20 BAB19 BAB18 BAB17 BAB16
Initial value: 0 0 0 0 0 0 0 0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
BARBL
Bit: 15 14 13 12 11 10 9 8
BAB15 BAB14 BAB13 BAB12 BAB11 BAB10 BAB9 BAB8
Initial value: 0 0 0 0 0 0 0 0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 7 6 5 4 3 2 1 0
BAB7 BAB6 BAB5 BAB4 BAB3 BAB2 BAB1 BAB0
Initial value: 0 0 0 0 0 0 0 0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Break address register B (BARB) consists of two 16-bit readable/writable registers: break address
register BH (BARBH) and break address register BL (BARBL). BARBH specifies the upper half
(bits 31 to 16) of the address used as a channel B break condition, and BARBL specifies the lower
half (bits 15 to 0). BARBH and BARBL are initialized to H'0000 by a power-on reset; after a
manual reset, their values are undefined.
BARBH Bits 15 to 0—Break Address B31 to B16 (BAB31 to BAB16): These bits store the upper
half (bits 31 to 16) of the address used as a channel B break condition.
BARBL Bits 15 to 0—Break Address B15 to B0 (BAB15 to BAB0): These bits store the lower
half (bits 15 to 0) of the address used as a channel B break condition.