Renesas SH7616, Руководство по оборудованию

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Section 6 User Break Controller (UBC)
Rev. 2.00 Mar 09, 2006 page 211 of 906
REJ09B0292-0200
6.2.7 Break Address Register C (BARC)
BARCH
Bit: 15 14 13 12 11 10 9 8
BAC31 BAC30 BAC29 BAC28 BAC27 BAC26 BAC25 BAC24
Initial value: 0 0 0 0 0 0 0 0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 7 6 5 4 3 2 1 0
BAC23 BAC22 BAC21 BAC20 BAC19 BAC18 BAC17 BAC16
Initial value: 0 0 0 0 0 0 0 0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
BARCL
Bit: 15 14 13 12 11 10 9 8
BAC15 BAC14 BAC13 BAC12 BAC11 BAC10 BAC9 BAC8
Initial value: 0 0 0 0 0 0 0 0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 7 6 5 4 3 2 1 0
BAC7 BAC6 BAC5 BAC4 BAC3 BAC2 BAC1 BAC0
Initial value: 0 0 0 0 0 0 0 0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Break address register C (BARC) consists of two 16-bit readable/writable registers: break address
register CH (BARCH) and break address register CL (BARCL). BARCH specifies the upper half
(bits 31 to 16) of the address used as a channel C break condition, and BARCL specifies the lower
half (bits 15 to 0). The address bus connected to the X/Y memory can also be specified as a break
condition by making a setting in the XYEC bit/XYSC bit in break bus cycle register C (BBRC).
When XYEC = 0, BAC31 to BAC0 specify the address. When XYEC = 1, the upper 16 bits
(BAC31 to BAC16) of BARC specify the X address bus, and the lower 16 bits (BAC15 to BAC0)
specify the Y address bus. BARCH and BARCL are initialized to H'0000 by a power-on reset;
after a manual reset, their values are undefined.