Renesas SH7616, Руководство по оборудованию

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Section 7 Bus State Controller (BSC)
Rev. 2.00 Mar 09, 2006 page 349 of 906
REJ09B0292-0200
7.9.1 Master Mode
The chip keeps the bus unless it receives a bus request. When a bus release request (
BRLS
)
assertion (low level) is received from an external device, buses are released and a bus grant (
BGR
)
is asserted (low level) as soon as the bus cycle being executed is completed. When it receives a
negated (high level)
BRLS
signal, indicating that the slave has released the bus, it negates the
BGR
(to high level) and begins using the bus. When the bus is released, all output and I/O signals
related to the bus interface are changed to high impedance, except for the CKE signal for the
synchronous DRAM interface, the
BGR
signal for bus arbitration, and DMA transfer control
signals DACK0 and DACK1.
When the DRAM has finished precharging, the bus is released. The synchronous DRAM also
issues a precharge command to the active bank. After this is completed, the bus is released.
The specific bus release sequence is as follows. First, the address bus and data bus become high
impedance synchronously with a rise of the clock. Half a cycle later, the bus use enable signal is
asserted synchronously with a fall of the clock. Thereafter the bus control signals (
BS
,
CSn
,
RAS
,
CASn
,
WEn
,
RD
, RD/
WR
) become high impedance at a rise of the clock. These bus control
signals are driven high at least 2 cycles before they become high impedance. Sampling for bus
request signals occurs at the clock fall.
The sequence when the bus is taken back from the slave is as follows. When the negation of
BRLS
is detected at a clock fall, high-level driving of the bus control signals starts half a cycle later. The
bus use enable signal is then negated at the next clock fall. The address bus and data bus are driven
starting at the next clock rise. The bus control signals are asserted and the bus cycle actually starts
from the same clock rise at which the address and data signals are driven, at the earliest. Figure
7.58 shows the timing of bus arbitration.
To reduce the overhead due to arbitration with a user-designed slave, a number of consecutive bus
accesses may be attempted. In this case, to insure dependable refreshing, the design must provide
for the slave to release the bus before it has held it for a period exceeding the refresh cycle. The
SH7616 is provided with the REFOUT pin to send a signal requesting the bus while refresh
execution is being kept waiting. REFOUT is asserted while refresh execution is being kept waiting
until the bus is acquired. When the external slave device receives this signal and releases the bus,
the bus is returned to the chip and refreshing can be executed.