Section 14 Serial Communication Interface with FIFO (SCIF)
Rev. 2.00 Mar 09, 2006 page 607 of 906
REJ09B0292-0200
End of transmission
Read TDFE bit in SC1SSR
Write {16 – (transmit trigger set
number)} bytes of transmit data
to SCFTDR, and set MPBT
in SC2SSR
TDFE = 1?
End of transmission?
Read TEND bit in SC2SSR
TEND = 1?
Break output?
Clear DR to 0
Clear TE bit to 0 in SCSCR,
and set TxD pin as output
port with PFC
Start of transmission
Initialization
Yes
No
No
No
No
Yes
Yes
Yes
1
2
3
4
1. PFC initialization: Set the TxD pin, and
the SCK pin if necessary, with the PFC.
2. SCIF status check and transmit data
write: Read the serial status 1 register
(SC1SSR) and check that the TDFE bit
is set to 1, then write transmit data to
the transmit FIFO data register
(SCFTDR). Set the MPBT bit to 0 or 1
in SC1SSR. Finally, clear the TDFE
and TEND flags to 0 after reading 1
from them.
The number of data bytes that can be
written is {16 – (transmit trigger set
number)}.
3. Serial transmission continuation
procedure: To continue serial
transmission, read 1 from the TDFE bit
to confirm that writing is possible, then
write data to SCFTDR, and then clear
the TDFE bit to 0. (Checking and
clearing of the TDFE bit is automatic
when the DMAC is activated by a
transmit-FIFO-data-empty interrupt
(TXI) request, and data is written to
SCFTDR.)
4. Break output at the end of serial
transmission: To output a break in
serial transmission, clear the port data
register (DR) to 0, then clear the TE bit
to 0 in SCSCR, and set the TxD pin as
an output port with the PFC.
In steps 2 and 3, the number of transmit
data bytes that can be written can be
ascertained from the number of transmit
data bytes in SCFTDR indicated in the
upper 8 bits of the FIFO data count register
(SCFDR).
Clear TDFE and TEND flags to 0
Figure 14.12 Sample Multiprocessor Serial Transmission Flowchart
Содержание SH7616
Страница 10: ...Rev 2 00 Mar 09 2006 page x of xxvi ...
Страница 132: ...Section 2 CPU Rev 2 00 Mar 09 2006 page 106 of 906 REJ09B0292 0200 ...
Страница 568: ...Section 12 16 Bit Free Running Timer FRT Rev 2 00 Mar 09 2006 page 542 of 906 REJ09B0292 0200 ...
Страница 582: ...Section 13 Watchdog Timer WDT Rev 2 00 Mar 09 2006 page 556 of 906 REJ09B0292 0200 ...
Страница 662: ...Section 14 Serial Communication Interface with FIFO SCIF Rev 2 00 Mar 09 2006 page 636 of 906 REJ09B0292 0200 ...
Страница 706: ...Section 16 Serial I O SIO Rev 2 00 Mar 09 2006 page 680 of 906 REJ09B0292 0200 ...
Страница 820: ...Section 19 Pin Function Controller PFC Rev 2 00 Mar 09 2006 page 794 of 906 REJ09B0292 0200 ...
Страница 932: ...Appendix D Package Dimensions Rev 2 00 Mar 09 2006 page 906 of 906 REJ09B0292 0200 ...
Страница 935: ...SH7616 Hardware Manual ...