Section 7 Bus State Controller (BSC)
Rev. 2.00 Mar 09, 2006 page 337 of 906
REJ09B0292-0200
Tdsww
Tc1
CKIO
A24–A16
A15–A1
RAS
CASn
RD/
WR
D31–D0
DACKn
*
Tc2
Low level
Note:
*
DACKn waveform when active-low is specified
Figure 7.50 DMA Single Transfer Mode Write Cycle Timing
(
RAS
RAS
RAS
RAS
Down Mode, Same Row Address)
7.6.8
Refreshing
The bus state controller includes a function for controlling DRAM refreshing. Distributed
refreshing using a
CAS
-before-
RAS
refresh cycle can be performed by clearing the RMODE bit to
0 and setting the RFSH bit to 1 in MCR. Consecutive refreshes can be generated by setting bits
RRC2–RRC0 in RTCSR. If DRAM is not accessed for a long period, self-refresh mode, which
uses little power consumption for data retention, can be activated by setting both the RMODE and
RFSH bits to 1.
CAS
CAS
CAS
CAS
-Before-
RAS
RAS
RAS
RAS
Refreshing:
Refreshing is performed at intervals determined by the input clock
selected by bits CKS2–CKS0 in RTCSR, and the value set in RTCOR. The RTCOR value and the
value of bits CKS2–CKS0 in RTCSR should be set so as to satisfy the refresh interval
Содержание SH7616
Страница 10: ...Rev 2 00 Mar 09 2006 page x of xxvi ...
Страница 132: ...Section 2 CPU Rev 2 00 Mar 09 2006 page 106 of 906 REJ09B0292 0200 ...
Страница 568: ...Section 12 16 Bit Free Running Timer FRT Rev 2 00 Mar 09 2006 page 542 of 906 REJ09B0292 0200 ...
Страница 582: ...Section 13 Watchdog Timer WDT Rev 2 00 Mar 09 2006 page 556 of 906 REJ09B0292 0200 ...
Страница 662: ...Section 14 Serial Communication Interface with FIFO SCIF Rev 2 00 Mar 09 2006 page 636 of 906 REJ09B0292 0200 ...
Страница 706: ...Section 16 Serial I O SIO Rev 2 00 Mar 09 2006 page 680 of 906 REJ09B0292 0200 ...
Страница 820: ...Section 19 Pin Function Controller PFC Rev 2 00 Mar 09 2006 page 794 of 906 REJ09B0292 0200 ...
Страница 932: ...Appendix D Package Dimensions Rev 2 00 Mar 09 2006 page 906 of 906 REJ09B0292 0200 ...
Страница 935: ...SH7616 Hardware Manual ...