Renesas H8S/2318 series, Руководство по оборудованию

Страница: 273 / 1121

Rev. 5.00, 12/03, page 243 of 1088
Port 3 Data Direction Register (P3DDR)
Bit : 7 6 5 4 3 2 1 0
— — P35DDR P34DDR P33DDR P32DDR P31DDR P30DDR
Initial value : Undefined Undefined 0 0 0 0 0 0
R/W : — — W W W W W W
P3DDR is an 8-bit write-only register, the individual bits of which specify input or output for the
pins of port 3. Bits 7 and 6 are reserved. P3DDR cannot be read; if it is, an undefined value will be
read.
Setting P3DDR bits to 1 makes the corresponding port 3 pins output pins, while clearing the bits
to 0 makes the pins input pins.
P3DDR is initialized to H'00 (bits 5 to 0) by a reset, and in hardware standby mode. It retains its
prior state after in software standby mode. As the SCI is initialized, the pin states are determined
by the P3DDR and P3DR specifications.
Port 3 Data Register (P3DR)
Bit : 7 6 5 4 3 2 1 0
— — P35DR P34DR P33DR P32DR P31DR P30DR
Initial value : Undefined Undefined 0 0 0 0 0 0
R/W : — — R/W R/W R/W R/W R/W R/W
P3DR is an 8-bit readable/writable register that stores output data for the port 3 pins (P35 to P30).
Bits 7 and 6 are reserved; they return an undetermined value if read, and cannot be modified.
P3DR is initialized to H'00 (bits 5 to 0) by a on reset, and in hardware standby mode. It retains its
prior state after in software standby mode.