Renesas H8S/2318 series, Руководство по оборудованию

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Rev. 5.00, 12/03, page 782 of 1088
•
The division ratio can be changed while the chip is operating. The clock output from the
φ
pin
will also change when the division ratio is changed. The frequency of the clock output from
the
φ
pin in this case will be as follows:
φ
= EXTAL
×
n
Where: EXTAL: Crystal resonator or external clock frequency
n: Division ratio (n =
φ
/2,
φ
/4, or
φ
/8)
•
Do not set the DIV bit and bits SCK2 to SCK0 simultaneously. First set the DIV bit, then bits
SCK2 to SCK0.
Bit 5
DIV
Description
0 When bits SCK2 to SCK0 are set to other than high-speed mode, medium-speed
mode is set
(Initial value)
1 When bits SCK2 to SCK0 are set to other than high-speed mode, a divided clock is
supplied to the entire chip
Bits 4 and 3—Reserved: These bits cannot be modified and are always read as 0.
Bits 2 to 0—System Clock Select 2 to 0 (SCK2 to SCK0): When the DIV bit is cleared to 0,
these bits select the bus master clock; when the DIV bit is set to 1, they select the division ratio of
the clock supplied to the entire chip.
Description
Bit 2
SCK2 Bit 1
SCK1 Bit 0
SCK0
DIV = 0 DIV = 1
0 0 0 Bus master is in high-speed
mode
(Initial value)
Bus master is in high-speed
mode
(Initial value)
1 Medium-speed clock is
φ
/2 Clock supplied to entire chip is
φ
/2
1 0 Medium-speed clock is
φ
/4 Clock supplied to entire chip is
φ
/4
1 Medium-speed clock is
φ
/8 Clock supplied to entire chip is
φ
/8
1 0 0 Medium-speed clock is
φ
/16 —
1 Medium-speed clock is
φ
/32 —
1 — — —