Renesas H8S/2318 series, Руководство по оборудованию

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Rev. 5.00, 12/03, page 412 of 1088
Bits 2 to 0—Clock Select 2 to 0 (CKS2 to CKS0): These bits select one of eight internal clock
sources, obtained by dividing the system clock (
φ
), for input to TCNT.
Description
Bit 2
CKS2 Bit 1
CKS1 Bit 0
CKS0
Clock Overflow Period (when
φφφφ
= 20 MHz)
*
0 0 0
φ
/2 (Initial value) 25.6
µ
s
1
φ
/64 819.2
µ
s
1 0
φ
/128 1.6 ms
1
φ
/512 6.6 ms
1 0 0
φ
/2048 26.2 ms
1
φ
/8192 104.9 ms
1 0
φ
/32768 419.4 ms
1
φ
/131072 1.68 s
Note: * The overflow period is the time from when TCNT starts counting up from H'00 until overflow
occurs.
11.2.3 Reset Control/Status Register (RSTCSR)
Bit : 7 6 5 4 3 2 1 0
WOVF RSTE — — — — — —
Initial value : 0 0 0 1 1 1 1 1
R/W : R/(W)
*
R/W R/W — — — — —
Note:
*
Only 0 can be written, to clear the flag.
RSTCSR is an 8-bit readable/writable* register that controls the generation of the internal reset
signal when TCNT overflows, and selects the type of internal reset signal.
RSTCSR is initialized to H'1F by a reset signal from the
RES
pin, but not by the WDT internal
reset signal caused by overflows.
Note: * RSTCSR is write-protected by a password to prevent accidental overwriting. For details
see section 11.2.4, Notes on Register Access.