Rev. 5.00, 12/03, page 20 of 1088
Pin No.
Type
Symbol
TFP-100B,
TFP-100G FP-100A
I/O
Name and Function
Interrupts
NMI
63
65
Input
Nonmaskable interrupt: Requests a
nonmaskable interrupt. When this pin
is not used, it should be fixed high.
IRQ7
to
IRQ0
94, 93,
13, 12,
73 to 76
96, 95,
15, 14,
75 to 78
Input
Interrupt request 7 to 0: These pins
request a maskable interrupt.
Address bus
A23 to
A0
2, 1,
100, 99,
53 to 50,
48 to 41,
39 to 32
4 to 1,
55 to 52,
50 to 43,
41 to 34
Output Address bus: These pins output an
address.
Data bus
D15 to
D0
30 to 19,
17 to 14
32 to 21,
19 to 16
I/O
Data bus: These pins constitute a
bidirectional data bus.
Bus control
CS7
to
CS0
94 to 97
75, 76
96 to 99
77, 78
Output Chip select: Signals for selecting
areas 7 to 0.
AS
70
72
Output Address strobe: When this pin is low,
it indicates that address output on
the address bus is enabled.
RD
71
73
Output Read: When this pin is low, it
indicates that the external address
space can be read.
HWR
72
74
Output High write: A strobe signal that writes
to external space and indicates that
the upper half (D15 to D8) of the data
bus is enabled.
LWR
73
75
Output Low write: A strobe signal that writes
to external space and indicates that
the lower half (D7 to D0) of the data
bus is enabled.
WAIT
74
76
Input
Wait: Requests insertion of a wait
state in the bus cycle when
accessing external 3-state access
space.
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