Renesas H8S/2318 series, Руководство по оборудованию

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Rev. 5.00, 12/03, page 175 of 1088
Relationship between Chip Select (
CS CS CS CS
) Signal and Read (
RD RD RD RD
) Signal: Depending on the
system’s load conditions, the
RD
signal may lag behind the
CS
signal. An example is shown in
figure 6-18.
In this case, with the setting for no idle cycle insertion (a), there may be a period of overlap
between the bus cycle A
RD
signal and the bus cycle B
CS
signal.
Setting idle cycle insertion, as in (b), however, will prevent any overlap between the
RD
and
CS
signals.
In the initial state after reset release, idle cycle insertion (b) is set.
T
1
Address bus
φ
RD
Bus cycle A
T
2
T
3
T
1
T
2
Bus cycle B
Possibility of overlap between
CS
(area B) and
RD
T
1
Address bus
φ
Bus cycle A
T
2
T
3
T
I
T
1
Bus cycle B
T
2
CS
(area A)
CS
(area B)
RD
CS
(area A)
CS
(area B)
(a) Idle cycle not inserted
(ICIS1 = 0)
(b) Idle cycle inserted
(ICIS1 = 1 (initial value))
Figure 6-18 Relationship between Chip Select (
CS CS CS CS
) and Read (
RD RD RD RD
)