Renesas H8S/2318 series, Руководство по оборудованию

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Rev. 5.00, 12/03, page 410 of 1088
11.2 Register Descriptions
11.2.1 Timer Counter (TCNT)
Bit : 7 6 5 4 3 2 1 0
Initial value : 0 0 0 0 0 0 0 0
R/W : R/W R/W R/W R/W R/W R/W R/W R/W
TCNT is an 8-bit readable/writable*
1
up-counter.
When the TME bit is set to 1 in TCSR, TCNT starts counting pulses generated from the internal
clock source selected by bits CKS2 to CKS0 in TCSR. When the count overflows (changes from
H'FF to H'00), either the watchdog timer overflow signal (
WDTOVF
)*
2
or an interval timer
interrupt (WOVI) is generated, depending on the mode selected by the WT/
IT
bit in TCSR.
TCNT is initialized to H'00 by a reset, in hardware standby mode, or when the TME bit is cleared
to 0. It is not initialized in software standby mode.
Notes: 1. TCNT is write-protected by a password to prevent accidental overwriting. For details
see section 11.2.4, Notes on Register Access.
2. The
WDTOVF
function is not available in the F-ZTAT versions.
11.2.2 Timer Control/Status Register (TCSR)
Bit : 7 6 5 4 3 2 1 0
OVF WT/
IT
TME — — CKS2 CKS1 CKS0
Initial value : 0 0 0 1 1 0 0 0
R/W : R/(W)
*
R/W R/W — — R/W R/W R/W
Note:
*
Only 0 can be written, to clear the flag.
TCSR is an 8-bit readable/writable* register. Its functions include selecting the clock source to be
input to TCNT, and the timer mode.
TCR is initialized to H'18 by a reset and in hardware standby mode. It is not initialized in software
standby mode.
Note: * TCSR is write-protected by a password to prevent accidental overwriting. For details see
section 11.2.4, Notes on Register Access.