Rev. 5.00, 12/03, page 179 of 1088
6.7.4
Transition Timing
Figure 6-19 shows the timing for transition to the bus released state.
CPU
cycle
External bus released state
CPU cycle
Address
T
0
T
1
T
2
φ
Address bus
Data bus
AS
HWR
,
LWR
BREQ
BACK
High impedance
Minimum
1 state
BREQO
*
[1]
[2]
[3]
[4]
[5]
[6]
[1]
[2]
[3]
[4]
[5]
[6]
Note:
*
Output only when BREQOE is set to 1.
Low level of
BREQ
pin is sampled at rise of T
2
state.
BACK
pin is driven low at end of CPU read cycle, releasing bus to external
bus master.
BREQ
pin state is still sampled in external bus released state.
High level of
BREQ
pin is sampled.
BACK
pin is driven high, ending bus release cycle.
BREQO
signal goes high 1.5 clocks after
BACK
signal goes high.
High impedance
High impedance
High impedance
RD
High impedance
Figure 6-19 Bus Released State Transition Timing
Содержание H8S/2318 series
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