Renesas H8S/2318 series, Руководство по оборудованию

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Rev. 5.00, 12/03, page 1017 of 1088
TCR0—Time Control Register 0 H'FFB0 8-Bit Timer Channel 0
TCR1—Time Control Register 1 H'FFB1 8-Bit Timer Channel 1
7
CMIEB
0
R/W
6
CMIEA
0
R/W
5
OVIE
0
R/W
4
CCLR1
0
R/W
3
CCLR0
0
R/W
0
CKS0
0
R/W
2
CKS2
0
R/W
1
CKS1
0
R/W
Note: *
0 0 0
1
Clock input disabled
Internal clock: counted at falling edge
of
φ
/8
Internal clock: counted at falling edge
of
φ
/64
1 0
Internal clock: counted at falling edge
of
φ
/8192
1
1 0 0 For channel 0:
Count at TCNT1 overflow signal
*
For channel 1:
Count at TCNT0 compare match A
*
External clock: counted at rising edge
External clock: counted at falling edge
1
0
1
External clock: counted at both rising and
falling edges
1
Clock Select
0
1
CMFB interrupt requests (CMIB) are disabled
CMFB interrupt requests (CMIB) are enabled
Compare Match Interrupt Enable B
0
1
CMFA interrupt requests (CMIA) are disabled
CMFA interrupt requests (CMIA) are enabled
Compare Match Interrupt Enable A
0
1
OVF interrupt requests (OVI) are disabled
OVF interrupt requests (OVI) are enabled
Timer Overflow Interrupt Enable
0
1
Clear is disabled
Clear by compare match A
Clear by compare match B
Clear by rising edge of external reset input
0
1
0
1
Counter Clear
Bit
Initial value
Read/Write
If the count input of channel 0 is the TCNT1 overflow
signal and that of channel 1 is the TCNT0 compare
match signal, no incrementing clock is generated.
Do not use this setting.
:
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