Renesas H8S/2318 series, Руководство по оборудованию

Страница: 962 / 1121

Rev. 5.00, 12/03, page 932 of 1088
Address
Register
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Module
Name
Data
Bus
Width
H'FFF0 TCR2 — CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 TPU2 16 bits
H'FFF1 TMDR2 — — — — MD3 MD2 MD1 MD0
H'FFF2 TIOR2 IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0
H'FFF4 TIER2 TTGE — TCIEU TCIEV — — TGIEB TGIEA
H'FFF5 TSR2 TCFD — TCFU TCFV — — TGFB TGFA
H'FFF6 TCNT2
H'FFF7
H'FFF8 TGR2A
H'FFF9
H'FFFA TGR2B
H'FFFB
Notes: 1. Located in on-chip RAM. The bus width is 32 bits when the DTC accesses this area as
register information, and 16 bits otherwise.
2. Valid only in the F-ZTAT versions but the H8S/2314 F-ZTAT. In the H8S/2314 F-ZTAT,
this cannot be used and must not be accessed.
3. Valid only in the F-ZTAT versions.
4. Functions as C/
A
for SCI use, and as GM for smart card interface use.
5. Functions as CHR for SCI use, and as BLK for smart card interface use.
6. Functions as STOP for SCI use, and as BCP1 for smart card interface use.
7. Functions as MP for SCI use, and as BCP0 for smart card interface use.
8. Functions as FER for SCI use, and as ERS for smart card interface use.
9. Valid in the H8S/2317 F-ZTAT only.
10. Valid in the H8S/2318 F-ZTAT only.
11. Valid in the H8S/2315 F-ZTAT, H8S/2314 F-ZTAT only.
12. Valid in the H8S/2319 F-ZTAT only.
13. Valid in the H8S/2319C F-ZTAT only.