Renesas H8S/2318 series, Руководство по оборудованию

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Rev. 5.00, 12/03, page 282 of 1088
Bits 7 and 6—Reserved: Only 0 should be written to these bits.
Bit 5—CS167 Enable (CS167E): Enables or disables
CS1
,
CS6
, and
CS7
output. For details, see
section 8.12, Port G.
Bit 4—CS25 Enable (CS25E): Enables or disables
CS2
,
CS3
,
CS4
, and
CS5
output. Change the
CS25E setting only when the DDR bits are cleared to 0. This bit is valid in modes 4 to 6.
Bit 4
CS25E
Description
0
CS2
,
CS3
,
CS4
, and
CS5
output disabled (can be used as I/O ports)
1
CS2
,
CS3
,
CS4
, and
CS5
output enabled (Initial value)
Bit 3—AS Output Disable (ASOD): Enables or disables
AS
output. This bit is valid in modes 4
to 6.
Bit 3
ASOD
Description
0 PF6 is used as
AS
output pin (Initial value)
1 PF6 is designated as I/O port, and does not function as
AS
output pin
Bits 2 to 0—Reserved: When read, these bits are always read as 0.
System Control Register (SYSCR)
Bit : 7 6 5 4 3 2 1 0
— — INTM1 INTM0 NMIEG LWROD — RAME
Initial value : 0 0 0 0 0 0 0 1
R/W : R/W — R/W R/W R/W R/W R/W R/W
Bit 2—LWR Output Disable (LWROD): Enables or disables
LWR
output. This bit is valid in
modes 4 to 6.
Bit 2
LWROD
Description
0 PF3 is designated as
LWR
output pin (Initial value)
1 PF3 is designated as I/O port, and does not function as
LWR
output pin