Renesas H8S/2318 series, Руководство по оборудованию

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Rev. 5.00, 12/03, page 244 of 1088
Port 3 Register (PORT3)
Bit : 7 6 5 4 3 2 1 0
— — P35 P34 P33 P32 P31 P30
Initial value : Undefined Undefined —
*
—
*
—
*
—
*
—
*
—
*
R/W : — — R R R R R R
Note: * Determined by state of pins P35 to P30.
PORT3 is an 8-bit read-only register that shows the pin states, and cannot be modified. Writing of
output data for the port 3 pins (P35 to P30) must always be performed on P3DR.
Bits 7 and 6 are reserved; they return an undetermined value if read, and cannot be modified.
If a port 3 read is performed while P3DDR bits are set to 1, the P3DR values are read. If a port 3
read is performed while P3DDR bits are cleared to 0, the pin states are read.
After a reset and in hardware standby mode, PORT3 contents are determined by the pin states, as
P3DDR and P3DR are initialized. PORT3 retains its prior state after in software standby mode.
Port 3 Open Drain Control Register (P3ODR)
Bit : 7 6 5 4 3 2 1 0
— — P35ODR P34ODR P33ODR P32ODR P31ODR P30ODR
Initial value : Undefined Undefined 0 0 0 0 0 0
R/W : — — R/W R/W R/W R/W R/W R/W
P3ODR is an 8-bit readable/writable register that controls the PMOS on/off status for each port 3
pin (P35 to P30).
Bits 7 and 6 are reserved; they return an undetermined value if read, and cannot be modified.
Setting P3ODR bits to 1 makes the corresponding port 3 pins NMOS open-drain output pins,
while clearing the bits to 0 makes the pins CMOS output pins.
P3ODR is initialized to H'00 (bits 5 to 0) by a reset, and in hardware standby mode. It retains its
prior state after in software standby mode.