Renesas H8S/2318 series, Руководство по оборудованию

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Rev. 5.00, 12/03, page 393 of 1088
10.3 Operation
10.3.1 TCNT Incrementation Timing
TCNT is incremented by input clock pulses (either internal or external).
Internal Clock: Three different internal clock signals (
φ
/8,
φ
/64, or
φ
/8192) divided from the
system clock (
φ
) can be selected, by setting bits CKS2 to CKS0 in TCR. Figure 10-2 shows the
count timing.
φ
Internal clock
Clock input
to TCNT
TCNT N
−
1 N N+1
Figure 10-2 Count Timing for Internal Clock Input
External Clock: Three incrementation methods can be selected by setting bits CKS2 to CKS0 in
TCR: at the rising edge, the falling edge, and both rising and falling edges.
Note that the external clock pulse width must be at least 1.5 states for incrementation at a single
edge, and at least 2.5 states for incrementation at both edges. The counter will not increment
correctly if the pulse width is less than these values.
Figure 10-3 shows the timing of incrementation at both edges of an external clock signal.