IX-10
Index
SCSI (Cont.)
MSG/ signal (MSG)
new phases on the SCSI bus
output control latch (SOCL)
output data latch (SODL)
parity errors and interrupts
parity/CRC error (PAR)
performance
phase
phase mismatch - initiator mode
receive rate
registers
reset condition (RST)
RST/ received (RST)
RST/ signal (RST)
SCRIPTS operation
sample instruction
SDP0/ parity signal (SDP0)
SDP1/ parity signal (SDP1)
selected as ID (SSAID[3:0])
selector ID (SSID)
send rate
single-ended
SODL register
status one (SSTAT1)
,
status two (SSTAT2)
status zero (SSTAT0)
,
synchronous offset maximum (SOM)
synchronous offset zero (SOZ)
synchronous operation
synchronous receive
synchronous send
termination
test four (STEST4)
test one (STEST1)
test three (STEST3)
test two (STEST2)
test zero (STEST0)
timer one (STIME1)
timer zero (STIME0)
timing diagrams
TolerANT technology
transfer (SXFER)
Ultra 160 features
Ultra160 SCSI
valid (VAL)
wide residue (SWIDE)
wide SCSI receive bit
wide SCSI send bit
SCSI-1
transfers (single-ended 5.0 Mbytes)
SCSI-2
fast transfers
second dword
,
select
during selection
instruction
with ATN/
with SATN/ on a start sequence (WATN)
selected (SEL)
,
selection or reselection time-out (STO)
selection response logic test (SLT)
semaphore (SEM)
send rate calculation
serial EEPROM
data format
interface
SERR/
SERR/enable (SE)
set instruction
SCRIPTS
set/clear
carry
SACK/
SATN/
target mode
SIDL
least significant byte full (ILF)
most significant byte full (ILF1)
SIEN0
SIEN1
signal process (SIGP)
signaled system error (SSE)
simple arbitration
single
address cycles
ended SCSI signals
step interrupt (SSI)
step mode (SSM)
transition
data-in
data-out
SIP
SIST0
SIST1
slow memory
read cycle
write cycle
slow ROM pin
SODL
least significant byte full (OLF)
most significant byte full (OLF1)
SODL register
software reset (SRST)
source
I/O-memory enable (SIOM)
special cycle command
SREQ
stacked interrupts
start
address
,
DMA operation (STD)
sequence (START)
static block move selector (SBMS)
status register
STOP command
stop signal
STOP/
store instruction
stress ratings
subsystem ID
(SID[15:0])
subsystem vendor ID
(SVID[15:0])
SureLINK
SWIDE register
SYNC_IRQD (SI)
synchronous
clock conversion factor (SCF[2:0])
data transfer rates
operation
Содержание LSI53C1000
Страница 6: ...vi Preface...
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Страница 28: ...1 12 Introduction...
Страница 234: ...4 124 Registers...
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Страница 350: ...6 76 Specifications Figure 6 42 LSI53C1000 329 Ball Grid Array Bottom view...
Страница 352: ...6 78 Specifications...
Страница 360: ...A 8 Register Summary...
Страница 376: ...IX 12 Index...