LSI LSI53C1000, Техническое руководство

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PCI Functional Description 2-13
If the corresponding cache command is not enabled, the cache logic falls
back to the next command enabled. For example, if the Memory Read
Multiple command is not enabled and the Memory Read Line command
is, Memory Read Line command is issued in place of Memory Read
Multiple command. If no cache commands are enabled, cache write
alignment still occurs but no cache commands are issued; only Memory
Reads and Memory Writes are issued.
2.1.3.3 Memory Read Caching
The type of Memory Read command issued depends on the starting
location of the transfer and the number of bytes to be transferred. During
reads, no cache alignment is done, as it is neither required nor optional
according to PCI 2.2 specification. Reads are a programmed burst length
in size, as set in the
DMA Mode (DMODE) and Chip Test Five (CTEST5)
registers. In the case of a transfer that is smaller than the burst length,
all bytes for that transfer are read in one PCI burst transaction. If the
transfer crosses a Dword boundary (A[1:0] = 0b00), a Memory Read Line
command is issued. If the transfer crosses a cache boundary, as
specified by the cache line size programmed into the PCI configuration
register, a Memory Read Multiple command is issued. If a transfer does
not cross a Dword or cache boundary or if cache mode is not enabled a
Memory Read command is issued.
2.1.3.4 Memory Write Caching
Memory Writes are aligned in a single burst transfer to reach a cache
boundary. At that point, Memory Write and Invalidate commands are
issued and continue at the burst length programmed into the
DMA Mode
(DMODE) register. Memory Write and Invalidate commands continue to
be issued as long as the remaining byte count is greater than the
Memory Write and Invalidate threshold. When the remaining byte count
drops below this threshold, a single Memory Write burst is issued to
complete the transfer.
In summary, the general pattern for PCI writes is:
•
A single Memory Write to align to a cache boundary
•
Multiple Memory Write and Invalidates
•
A single data residual Memory Write to complete the transfer