LSI LSI53C1000, Техническое руководство

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PCI Bus Interface Signals 3-5
3.3.1 System Signals
Table 3.2 describes the signals for the System Signals group.
Table 3.2 System Signals
Name Bump Type Strength Description
CLK H3 I N/A Clock provides timing for all transactions on the PCI bus
and is an input to every PCI device. All other PCI signals
are sampled on the rising edge of CLK and other timing
parameters are defined with respect to this edge.
ENABLE66 B3 I N/A Enable66 controls the 66C bit in the PCI Configuration
Space. This bit indicates whether or not the chip is 66 MHz
capable. This pin has a static pull-up.
M66EN B1 I N/A M66EN is used to enable the 66 MHz PCI mode. This pin
is connected to the M66EN PCI signal on the PCI bus. This
pin has a static pull-up.
RST/ G1 I N/A Reset forces the PCI sequencer of each device to a known
state. All T/S and S/T/S signals are forced to a high
impedance state, and all internal logic is reset. The RST/
input is synchronized internally to the rising edge of CLK.
To properly reset the device, the CLK input must be active
while RST/ is active.