LSI LSI53C1000, Техническое руководство

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PCI and External Memory Interface Timing Diagrams 6-13
Table 6.16 and Figure 6.10 provide Interrupt Output timing data.
Figure 6.10 Interrupt Output
6.4 PCI and External Memory Interface Timing Diagrams
Figure 6.11 through Figure 6.34 and tables 6.17 through 6.38 represent
signal activity when the LSI53C1000 accesses the PCI bus. This section
includes timing diagrams for access to three groups of memory
configurations. The first group applies to Target Timing. The second
group applies to Initiator Timing. The third group applies to External
Memory Timing.
Note: Multiple byte accesses to the external memory bus
increase the read or write cycle by 11 clocks for each
additional byte.
Timing diagrams included in this section are:
•
Target Timing
– PCI Configuration Register Read
– PCI Configuration Register Write
– Operating Registers/SCRIPTS RAM Read, 32 Bits
– Operating Register/SCRIPTS RAM Read, 64 Bits
Table 6.16 Interrupt Output
Symbol Parameter Min Max Units
t
1
CLK HIGH to IRQ/ LOW 2 11 ns
t
2
CLK HIGH to IRQ/ HIGH 2 11 ns
t
3
IRQ/ deassertion time 3 – CLK
t
1
t
2
t
3
IRQ/
CLK