LSI LSI53C1000, Техническое руководство

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4-56 Registers
These bits steer the contents of the Chip Test Six
(CTEST6) register to the appropriate byte lane of the
64-bit DMA FIFO. If the FBL3 bit is set, then FBL2
through FBL0 determine which of eight byte lanes can be
read or written. When cleared, the byte lane read or
written is determined by the current contents of the
DMA
Next Address (DNAD) and DMA Byte Counter (DBC)
registers. Each of the eight bytes that make up the 64-bit
DMA FIFO is accessed by writing these bits to the proper
value. For normal operation, FBL3 must equal zero.
Register: 0x22
Chip Test Five (CTEST5)
Read/Write
ADCK Clock Address Incrementor 7
Setting this bit increments the address pointer contained
in the
DMA Next Address (DNAD) register. The DNAD
register is incremented based on the DNAD contents and
the current
DMA Byte Counter (DBC) value. This bit
automatically clears itself after incrementing the DNAD
register.
BBCK Clock Byte Counter 6
Setting this bit decrements the byte count contained in
the 24-bit
DMA Byte Counter (DBC) register. It is
decremented based on the DBC contents and the current
DMA Next Address (DNAD) value. This bit automatically
clears itself after decrementing the DBC register.
1 1 0 0 4 D[39:32]
1 1 0 1 5 D[47:40]
1 1 1 0 6 D[53:48]
1 1 1 1 7 D[63:54]
FBL3 FBL2 FBL1 FBL0
DMA FIFO
Byte Lane
Pins
7 6 5 3 2 1 0
ADCK BBCK R BL2 R
0 0 0 0 0 0 0 0