Index
IX-5
DEVSEL/
timing (DT[1:0])
DIEN
differential mode
DIP
direct
disable
auto FIFO clear (DISFC)
CRC checking
CRC protocol checking
dual address cycle (DDAC)
halt on parity/CRC error or ATN (target only) (DHP)
single initiator response (DSI)
disable internal SCRIPT RAM cycles
disconnect
instruction
DMA
byte counter (DBC)
command (DCMD)
control (DCNTL)
,
FIFO
,
(DF[7:0])
empty (DFE)
sections
interrupt
enable (DIEN)
,
interrupt pending (DIP)
mode (DMODE)
,
,
next address (DNAD)
next address 64 (DNAD64)
SCRIPTS
pointer (DSP)
pointer save (DSPS)
status (DSTAT)
,
,
domain validation
double transition
clocking
download mode
DSA
relative
relative selector (DRS)
DSPS register
DSTAT
DT data-in
DT data-out
DT transfers
configuration
dual address cycles
command
dynamic block move selector (DBMS)
E
EEPROM
default download mode
enable
64-bit
direct BMOV (EN64DBMV)
table indirect BMOV (EN64TIBMV)
AIP
asynchronous information protection
bus mastering (EBM)
I/O space (EIS)
jump on nondata phase mismatches (ENNDJ)
memory space (EMS)
parity
checking
checking (EPC)
error response (EPER)
phase mismatch jump (ENPMJ)
read
line (ERL)
multiple (ERMP)
response to
reselection (RRE)
selection (SRE)
wide SCSI (EWS)
ENABLE66
Enable66
enabling cache mode
encoded
chip SCSI ID (ENC[3:0])
destination SCSI ID
(ENC[3:0])
(ENID[3:0])
SCSI destination ID
entry storage address (ESA)
error reporting signals
even parity
expansion ROM base address
external
clock
memory
configuration
diagram examples
multiple byte accesses
read
timing
write
F
fast back to back capable
fatal interrupt
fetch enable (FE)
FIFO
byte control (FBL[2:0])
byte control (FBL3)
first dword
,
,
flush DMA FIFO (FLF)
flushing (FLSH)
FRAME/
full arbitration, selection/reselection
function complete (CMP)
,
G
general description
general purpose
(GPREG)
I/O (GPIO[4:0])
I/O pin 0
I/O pin 1
I/O pin 2
I/O pin 3
I/O pin 4
pin control (GPCNTL)
timer expired (GEN)
,
timer period (GEN[3:0])
timer scale factor (GENSF)
GNT/
GPIO enable (GPIO[1:0])
Содержание LSI53C1000
Страница 6: ...vi Preface...
Страница 16: ...xvi Contents...
Страница 28: ...1 12 Introduction...
Страница 234: ...4 124 Registers...
Страница 314: ...6 40 Specifications This page intentionally left blank...
Страница 318: ...6 44 Specifications This page intentionally left blank...
Страница 344: ...6 70 Specifications This page intentionally left blank...
Страница 350: ...6 76 Specifications Figure 6 42 LSI53C1000 329 Ball Grid Array Bottom view...
Страница 352: ...6 78 Specifications...
Страница 360: ...A 8 Register Summary...
Страница 376: ...IX 12 Index...