LSI LSI53C1000, Техническое руководство

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2-32 Functional Description
•
On every Store instruction
The Store instruction may also be used to place modified code
directly into memory. To avoid inadvertently flushing the prefetch unit
contents, use the No Flush option for all Store operations that do not
modify code within the next 8 Dwords.
•
On every write to the DMA SCRIPTS Pointer (DSP) register.
•
On all Transfer Control instructions, when the transfer conditions are
met.
This is necessary since the next instruction to be executed is not the
sequential next instruction in the prefetch unit.
•
When the Prefetch Flush bit ( DMA Control (DCNTL) register, bit 6)
is set.
The unit flushes whenever this bit is set. This bit is self-clearing.
2.2.7 Opcode Fetch Burst Capability
Setting the Burst Opcode Fetch Enable bit (bit 1) in the DMA Mode
(DMODE) register (0x38) causes the LSI53C1000 to burst in the first two
Dwords of all instruction fetches. If the instruction is a Memory-to-
Memory Move, the third Dword is accessed in a separate ownership. If
the instruction is an indirect type, the additional Dword is accessed in a
subsequent bus ownership. If the instruction is a Table Indirect Block
Move, the device uses two accesses, each a two Dword burst, to obtain
the four Dwords required.
Note: This feature is only useful if Prefetching is disabled.
This feature is only useful if fetching SCRIPTS instructions
from main memory. Due to the short access time of
SCRIPTS RAM, burst opcode fetching is not necessary
when fetching instructions from SCRIPTS RAM.
2.2.8 Load and Store Instructions
The LSI53C1000 supports the Load and Store instruction type, which
simplifies data movement between memory and the internal registers. It
also enables the chip to transfer bytes to addresses relative to the
Data
Structure Address (DSA) register. Load/Store data transfers to or from
the SCRIPTS RAM remain internal to the chip and do not generate PCI
bus cycles. While a Load/Store to or from SCRIPTS RAM is occurring,