LSI LSI53C1000, Техническое руководство

Страница: 200 / 384

4-90 Registers
phase referred to here is the phase encoded in the block
move SCRIPTS instruction, not the phase on the SCSI
bus that caused the phase mismatch.
ENNDJ Enable Jump On Nondata Phase Mismatches 5
This bit controls whether or not a jump is taken during a
nondata phase mismatch (Message-In, Message-Out,
Status, or Command). When this bit is cleared, jumps will
only be taken on Data-In or Data-Out phases, and a
phase mismatch interrupt will be generated for all other
phases. When this bit is set, jumps will be taken
regardless of the phase in the block move. Note that the
phase referred to here is the phase encoded in the block
move SCRIPTS instruction, not the phase on the SCSI
bus that caused the phase mismatch.
DISFC Disable Auto FIFO Clear 4
This bit controls whether or not the FIFO is automatically
cleared during a Data-Out phase mismatch. When set,
data in the DMA FIFO and data in the
SCSI Output Data
Latch (SODL) and SODR (a hidden buffer register which
is not accessible) registers are not cleared after
calculations on them are complete. When cleared, the
DMA FIFO, SODL, and SODR are automatically cleared.
This bit also disables the enhanced flushing mechanism.
R Reserved [3:2]
DISRC Disable Internal SCRIPTS RAM Cycles 1
This bit controls whether or not data transfers, for which
the source/destination is located in SCRIPTS RAM,
generate external PCI cycles.
If cleared, data transfers of this type do NOT generate
PCI cycles and stay internal to the chip. If set, data
transfers of this type generate PCI cycles. This does not
affect SCRIPTS Fetch operations from SCRIPTS RAM,
including Table Indirect and Indirect opcode fetches.
R Reserved 0