PCI and External Memory Interface Timing Diagrams
6-53
Figure 6.29 Normal/Fast Memory (
≥
128 Kbytes) Multiple Byte Access Read Cycle
(Cont.)
CLK
(Driven by System)
PAR
(Driven by LSI53C1000-
IRDY/
(Driven by Master)
TRDY/
(Driven by LSI53C1000)
STOP/
(Driven by LSI53C1000)
DEVSEL/
(Driven by LSI53C1000)
AD[31:0]
(Driven by LSI53C1000-
C_BE[3:0]/
(Driven by Master)
FRAME/
(Driven by Master)
Master-Addr; Data)
Master-Addr;-Data)
MAD
(Addr Driven by LSI53C1000
MAS1/
(Driven by LSI53C1000)
MAS0/
(Driven by LSI53C1000)
MCE/
(Driven by LSI53C1000)
MOE/
(Driven by LSI53C1000)
MWE/
(Driven by LSI53C1000)
17
18
19
20 21
22
23
24
25
26
27
28
29 30
31
Byte Enable
Data Driven by Memory)
16
32
33
Data Out
Out
Data In
Low Order
Address
Data In
Содержание LSI53C1000
Страница 6: ...vi Preface...
Страница 16: ...xvi Contents...
Страница 28: ...1 12 Introduction...
Страница 234: ...4 124 Registers...
Страница 314: ...6 40 Specifications This page intentionally left blank...
Страница 318: ...6 44 Specifications This page intentionally left blank...
Страница 344: ...6 70 Specifications This page intentionally left blank...
Страница 350: ...6 76 Specifications Figure 6 42 LSI53C1000 329 Ball Grid Array Bottom view...
Страница 352: ...6 78 Specifications...
Страница 360: ...A 8 Register Summary...
Страница 376: ...IX 12 Index...