LSI LSI53C1000, Техническое руководство

Страница: 113 / 384

PCI Configuration Registers 4-3
Registers: 0x02–0x03
Device ID
Read Only
DID Device ID [15:0]
This 16-bit register identifies the particular device. The
LSI53C1000 Device ID is 0x0021.
Registers: 0x04–0x05
Command
Read/Write
The SCSI Command register provides coarse control over a device’s
ability to generate and respond to PCI cycles. When a zero is written to
this register, the LSI53C1000 is logically disconnected from the PCI bus
for all accesses except configuration accesses.
R Reserved [15:9]
SE SERR/Enable 8
When this bit is set, the LSI53C1000 enables the SERR/
driver. SERR/ is disabled when this bit is cleared. The
default value of this bit is zero. This bit and bit 6 must be
set to report address parity errors.
R Reserved 7
EPER Enable Parity Error Response 6
When this bit is set, the LSI53C1000 detects parity errors
on the PCI bus and reports these errors to the system.
Only data parity checking is affected with this bit. The
LSI53C1000 always generates parity for the PCI bus.
15 0
DID
0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1
15 9 8 7 6 5 4 3 2 1 0
R SE R EPER R WIE R EBM EMS EIS
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0