LSI LSI53C1000, Техническое руководство

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2-8 Functional Description
2.1.2.12 Memory Read Line Command
This command is identical to the Memory Read command, except it
additionally indicates that the master intends to fetch a complete cache
line. This command is intended for use with bulk sequential data
transfers where the memory system and the requesting master might
gain some performance advantage by reading to a cache line boundary
rather than a single memory cycle. The Read Line function in the
LSI53C1000 takes advantage of the PCI 2.2 specification regarding
issuance of this command.
If the cache mode is disabled, no Read Line commands are issued.
If the cache mode is enabled, a Read Line command is issued on all
read cycles, except nonprefetch opcode fetches, when the following
conditions are met:
•
The CLSE bit (Cache Line Size Enable, bit 7, of the DMA Control
(DCNTL) register) is set.
•
The ERL bit (Enable Read Line, bit 3, of the DMA Mode (DMODE)
register) is set.
•
The Cache Line Size (CLS) register must contain a legal burst size
value (8, 16, 32, 64, or 128 Dwords) that is less than or equal to the
DMODE burst size.
•
The transfer crosses a Dword boundary, but not a cache line
boundary.
When these conditions are met, the chip issues a Read Line command
instead of a Memory Read during all PCI read cycles. Otherwise, it
issues a normal Memory Read command.
Read Multiple with Read Line Enabled – When both the Read
Multiple and Read Line modes are enabled, the Read Line command is
not issued if the above conditions are met. Instead, a Read Multiple
command is issued.
If the Read Multiple mode is enabled, Read Multiple commands are
issued if the Read Multiple conditions are met.