SCSI Registers
4-41
•
During a Transfer Control instruction, the Compare
Data (bit 18) and Compare Phase (bit 17) bits are set
in the
register while the
LSI53C1000 is in target mode.
•
During a Transfer Control instruction, the Carry Test
bit (bit 21) is set and either the Compare Data (bit 18)
or Compare Phase (bit 17) bit is set.
•
A Transfer Control instruction is executed with the
Wait for Valid phase bit (bit 16) set while the chip is in
the target mode.
•
A Load and Store instruction is issued with the
memory address mapped to the operating registers of
the chip, not including ROM or RAM.
•
A Load and Store instruction is issued when the
register address is not aligned with the memory
address.
•
A Load and Store instruction is issued with bit 5 in the
register cleared or bits 3 or
2 set.
•
A Load and Store instruction is issued when the count
value in the
register is not
set at 1, 2, 3, or 4.
•
A Load and Store instruction attempts to cross a
Dword boundary.
•
A Memory Move instruction is executed with one of
the reserved bits in the
register set.
•
A Memory Move instruction is executed with the
source and destination addresses not aligned.
•
A 64-bit Table Indirect Block Move instruction is
executed with a selector index value greater than
0x16.
•
If the Select with ATN/ bit, bit 24, is set for any I/O
instruction other than a Select instruction.
Содержание LSI53C1000
Страница 6: ...vi Preface...
Страница 16: ...xvi Contents...
Страница 28: ...1 12 Introduction...
Страница 234: ...4 124 Registers...
Страница 314: ...6 40 Specifications This page intentionally left blank...
Страница 318: ...6 44 Specifications This page intentionally left blank...
Страница 344: ...6 70 Specifications This page intentionally left blank...
Страница 350: ...6 76 Specifications Figure 6 42 LSI53C1000 329 Ball Grid Array Bottom view...
Страница 352: ...6 78 Specifications...
Страница 360: ...A 8 Register Summary...
Страница 376: ...IX 12 Index...