SCSI Functional Description
2-37
2.2.12 SCSI Data Paths
The data path through the LSI53C1000 is dependent on whether data is
moved into or out of the chip and whether the SCSI data transfer is
asynchronous or synchronous.
illustrates how data is moved
to and from the SCSI bus in each of the different modes. The following
sections determine if any bytes remain in the data path when the device
halts an operation.
Figure 2.3
LSI53C1000 Host Interface SCSI Data Paths
2.2.12.1 Asynchronous SCSI Send
To determine the number of bytes remaining in the DMA FIFO when a
phase mismatch occurs, read the
register. This 16-bit read only register contains the actual number of
bytes remaining in the DMA FIFO. In addition, the
register must be checked to determine if it contains any
remaining bytes. If bit 5 (OLF) in the
register
is set, then the least significant byte in the SODL register contains data.
If bit 5 (OLF1) in the
register is set, then the
most significant byte in the SODL register contains data. Checking these
bits also reveals bytes left in the SODL register from a Chained Move
PCI Interface
DMA FIFO
SODL Register
SCSI Interface
PCI Interface
DMA FIFO
SIDL Register
SCSI Interface
PCI Interface
DMA FIFO
SCSI Interface
PCI Interface
DMA FIFO
SCSI Interface
SCSI FIFO
Asynchronous
SCSI Send
Asynchronous
SCSI Receive
Synchronous
SCSI Send
Synchronous
SCSI Receive
SWIDE Register
Chain Byte
Holding Register
SWIDE Register
Содержание LSI53C1000
Страница 6: ...vi Preface...
Страница 16: ...xvi Contents...
Страница 28: ...1 12 Introduction...
Страница 234: ...4 124 Registers...
Страница 314: ...6 40 Specifications This page intentionally left blank...
Страница 318: ...6 44 Specifications This page intentionally left blank...
Страница 344: ...6 70 Specifications This page intentionally left blank...
Страница 350: ...6 76 Specifications Figure 6 42 LSI53C1000 329 Ball Grid Array Bottom view...
Страница 352: ...6 78 Specifications...
Страница 360: ...A 8 Register Summary...
Страница 376: ...IX 12 Index...