LSI LSI53C1000, Техническое руководство

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SCSI Registers 4-57
R Reserved [5:3]
BL2 Burst Length Bit 2 2
This bit works with bits 6 and 7 (BL[1:0]) in the DMA
Mode (DMODE) register to determine the burst length.
For complete definitions of this field, refer to the
descriptions of DMODE bits 6 and 7.
R Reserved [1:0]
Register: 0x23
Chip Test Six (CTEST6)
Read/Write
DF DMA FIFO [7:0]
Writing to this register writes data to the appropriate byte
lane of the DMA FIFO, as determined by the FBL bits in
the
Chip Test Four (CTEST4) register. Reading this
register unloads data from the appropriate byte lane of
the DMA FIFO, as determined by the FBL bits in the
CTEST4 register. Data written to the FIFO is loaded into
the top of the FIFO. Data read out of the FIFO is taken
from the bottom. To prevent DMA data from being
corrupted, this register should not be accessed before
starting or restarting SCRIPTS operations. This register
should be the last register read when performing register
dumps because of its effects on other registers. Write to
this register only when testing the DMA FIFO using the
CTEST4 register. Writing to this register while the test
mode is not enabled produces unexpected results.
7 0
DF
0 0 0 0 0 0 0 0