LSI LSI53C1000, Техническое руководство

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Load and Store Instructions 5-39
DSA DSA Relative 28
When this bit is cleared, the value in the DMA SCRIPTS
Pointer Save (DSPS) is the actual 32-bit memory address
used to perform the Load/Store to/from. When this bit is
set, the chip determines the memory address to perform
the Load/Store to/from by adding the 24-bit signed offset
value in the
DMA SCRIPTS Pointer Save (DSPS) to the
Data Structure Address (DSA) .
R Reserved [27:26]
NF No Flush (Store instruction only) 25
When this bit is set, the LSI53C1000 performs a Store
without flushing the prefetch unit. When this bit is cleared,
the Store instruction automatically flushes the prefetch
unit. Use No Flush if the source and destination are not
within four instructions of the current Store instruction.
This bit has no effect on the Load instruction.
Note: This bit has no effect unless the Prefetch Enable bit in the
DMA Control (DCNTL) register is set. For information on
SCRIPTS instruction prefetching, see Chapter 2, “Func-
tional Description.”
LS Load/Store 24
When this bit is set, the instruction is a Load. When
cleared, it is a Store.
A[7:0] Register Address [23:16]
A[7:0] selects the register to load/store to/from within the
LSI53C1000.
R Reserved [15:3]
BC Byte Count [2:0]
This value is the number of bytes to load/store.
5.7.2 Second Dword
This section describes the second Dword of the Load and Store
Instruction register.