Juniper QFX3000-G QFabric, Руководство по развертыванию, Страница: 364 / 652

Table 89: Node Device Port Mappings (continued)
Virtual Chassis VC1 Virtual Chassis VC0 Node Device
C1 to ge-0/0/7 C0 to ge-0/0/7 Node7
Figure 86 on page 338 shows the specific ports on the members of the first Virtual Chassis
that you must connect to the members of the second Virtual Chassis. These connections
create a link aggregation bundle (LAG) that provides redundancy and resiliency for the
Virtual Chassis portion of the control plane. In general, connect each 10-Gigabit Ethernet
uplink port from the first Virtual Chassis to the corresponding 10-Gigabit Ethernet uplink
port on the second Virtual Chassis.
Figure 86: QFX3000-G QFabric System Fiber-Based Control
Plane—Inter-Virtual Chassis LAG Connections
VC0
VC1
xe-1/1/0
xe-2/1/0
xe-3/1/0
xe-0/1/0
xe-1/1/0
xe-2/1/0
xe-3/1/0
xe-0/1/0
xe-4/1/0
xe-5/1/0
xe-6/1/0
xe-7/1/0
xe-4/1/0
xe-5/1/0
xe-6/1/0
xe-7/1/0
In this specific example, for Virtual Chassis VC0, connect port xe-0/1/0 to Virtual Chassis
VC1 port xe-0/1/0. For the remaining seven 10-Gigabit Ethernet uplink ports, connect
each port from VC0 to the corresponding port on VC1. For example, you would connect
the xe-1/1/0 port on VC0 to port xe-1/1/0 on VC1, and so on.
Table 83 on page 295 shows the full set of port mappings for the Virtual Chassis LAG
connections in this example.
Table 90: Virtual Chassis LAG Port Mappings
Member 7 Member 6 Member 5 Member 4 Member 3 Member 2 Member 1 Member 0
VC0 and
VC1
xe-7/1/0 to
xe-7/1/0 xe-6/1/0 to
xe-6/1/0 xe-5/1/0 to
xe-5/1/0 xe-4/1/0 to
xe-4/1/0 xe-3/1/0 to
xe-3/1/0 xe-2/1/0 to
xe-2/1/0 xe-1/1/0 to
xe-1/1/0 xe-0/1/0 to
xe-0/1/0 Uplink
port 0
Copyright © 2015, Juniper Networks, Inc. 338
QFX3000-G QFabric System Deployment Guide