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Contents

2.5.1

Interrupts

2-39

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.5.2

Branches, Calls, and Returns

2-39

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.5.3

Repeating a Single Instruction

2-39

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.5.4

Instruction Pipeline

2-40

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.6

Multiply Operations

2-41

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.6.1

16-bit X 16-bit Multiplication

2-41

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.6.2

32-Bit X 32-Bit Multiplication

2-42

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.7

Shift Operations

2-44

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CPU Interrupts and Reset

3-1

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Describes the TMS320C28x interrupts and how they are handled by the CPU. Also
explains the effects of a hardware reset.

3.1

CPU Interrupts Overview

3-2

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.2

CPU Interrupt Vectors and Priorities

3-4

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.3

Maskable Interrupts: INT1

−

INT14, DLOGINT, and RTOSINT

3-6

. . . . . . . . . . . . . . . . . . . . .

3.3.1

CPU Interrupt Flag Register (IFR)

3-7

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.3.2

CPU Interrupt Enable Register (IER) and

CPU Debug Interrupt Enable Register (DBGIER)

3-8

. . . . . . . . . . . . . . . . . . . . . . . .

3.4

Standard Operation for Maskable Interrupts

3-11

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.5

Nonmaskable Interrupts

3-17

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.5.1

INTR Instruction

3-17

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.5.2

TRAP Instruction

3-18

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.5.3

Hardware Interrupt NMI

3-21

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.6

Illegal-Instruction Trap

3-22

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.7

Hardware Reset (RS)

3-23

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Pipeline

4-1

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Describes the phases and operation of the instruction pipeline.

4.1

Pipelining of Instructions

4-2

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.1.1

Decoupled Pipeline Segments

4-4

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.1.2

Instruction-Fetch Mechanism

4-4

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.1.3

Address Counters FC, IC, and PC

4-5

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.2

Visualizing Pipeline Activity

4-7

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.3

Freezes in Pipeline Activity

4-10

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.3.1

Wait States

4-10

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.3.2

Instruction-Not-Available Condition

4-10

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.4

Pipeline Protection

4-12

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.4.1

Protection During Reads and Writes to the Same Data-Space Location

4-12

. . . .

4.4.2

Protection Against Register Conflicts

4-13

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.5

Avoiding Unprotected Operations

4-16

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.5.1

Unprotected Program-Space Reads and Writes

4-16

. . . . . . . . . . . . . . . . . . . . . . . .

4.5.2

An Access to One Location That Affects Another Location

4-16

. . . . . . . . . . . . . . .

4.5.3

Write Followed By Read Protection Mode

4-17

. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

C28x Addressing Modes

5-1

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Describes the addressing modes of the C28x.

5.1

Types of Addressing Modes

5-2

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Summary of Contents for TMS320C28x

Page 1: ...TMS320C28x DSP CPU and Instruction Set Reference Guide Literature Number SPRU430D August 2001 Revised March 2004...

Page 2: ...ute a license from TI to use such products or services or a warranty or endorsement thereof Use of such information may require a license from a third party under the patents or other intellectual pro...

Page 3: ...status registers ST0 and ST1 Chapter 3 Interrupts and Reset This chapter describes the interrupts and how they are handled by the CPU The chapter also explains the effects of a reset on the CPU and i...

Page 4: ...pendix E C2xLP Instruction Set Compatibility This appendix describes the instruction set compatibility with the C2xLP Appendix F Migration From C27x to C28x This appendix explains how to migrate code...

Page 5: ...l number 40 would be shown as 4016 An excep tion to this rule is a hexadecimal number in a code example these hexade cimal numbers have the suffix h For example the number 40 in the follow ing code is...

Page 6: ...he instruction set and the on chip peripherals TMS320C28x Assembly Language Tools User s Guide literature number SPRU513 describes the assembly language tools assembler and other tools used to develop...

Page 7: ...0C28x Enhanced Controller Area Network eCAN Reference Guide literature number SPRU074 describes the eCAN that uses es tablished protocol to communicate serially with other controllers in elec trically...

Page 8: ...programmed bit transfer rate The SPI is used for communications be tween the DSP controller and external peripherals or another controller TMS320C28x System Control and Interrupts Reference Guide lit...

Page 9: ...a Buses 1 9 1 4 2 Special Bus Operations 1 10 1 4 3 Alignment of 32 Bit Accesses to Even Addresses 1 11 2 Central Processing Unit 2 1 Describes the registers and primary functions of the TMS320C28x CP...

Page 10: ...INTR Instruction 3 17 3 5 2 TRAP Instruction 3 18 3 5 3 Hardware Interrupt NMI 3 21 3 6 Illegal Instruction Trap 3 22 3 7 Hardware Reset RS 3 23 4 Pipeline 4 1 Describes the phases and operation of th...

Page 11: ...tions used and describes each instruction in detail in alphabetical order 6 1 Instruction Set Summary Organized by Function 6 2 6 2 Register Operations 6 4 7 Emulation Features 7 1 Explains features s...

Page 12: ...nhancements of the C28x over the C2xLP C 2 C 2 Registers C 3 C 2 1 CPU Register Changes C 4 C 2 2 Data Page DP Pointer Changes C 5 C 2 3 Status Register Changes C 7 C 2 4 Register Reset Conditions C 1...

Page 13: ...6 F 1 4 C27x Object Compatibility F 8 F 2 Moving to a C28x Object F 9 F 2 1 Caution When Changing OJBMODE F 9 F 3 Migrating to C28x Object Code F 11 F 3 1 Instruction Syntax Changes F 11 F 3 2 Repeata...

Page 14: ...terrupt Flag Register IFR 3 7 3 2 Interrupt Enable Register IER 3 9 3 3 Debug Interrupt Enable Register DBGIER 3 10 3 4 Standard Operation for CPU Maskable Interrupts 3 12 3 5 Functional Flow Chart fo...

Page 15: ...en C2xLP and C28x C 7 C 4 Memory Map Comparison See Note A C 13 D 1 Flow Chart of Recommended Migration Steps D 4 F 1 C28x Registers F 2 F 2 Full Context Save Restore F 5 F 3 Code for a Full Context S...

Page 16: ...Maskable Interrupt 3 7 3 3 Register Pairs Saved and SP Positions for Context Saves 3 14 3 4 Register Pairs Saved and SP Positions for Context Saves 3 20 3 5 Registers After Reset 3 23 5 1 Addressing M...

Page 17: ...28x Differences in Interrupts D 10 D 7 C2xLP and C28x Differences in Status Registers D 11 D 8 C2xLp and C28x Differences in Memory Maps D 12 D 9 C2xLP and C28x Differences in Instructions and Registe...

Page 18: ...6 4 2 Diagramming Pipeline Activity 4 8 4 3 Simplified Diagram of Pipeline Activity 4 9 4 4 Conflict Between a Read From and a Write to Same Memory Location 4 13 4 5 Register Conflict 4 14 7 1 Initial...

Page 19: ...the C2xLP CPU can be reassembled to run on a C28x device The C2xLP CPU is used in all TMS320F24xx and TMS320C20x DSPs and their derivatives This document refers to C2xLP as a generic name for the DSP...

Page 20: ...ses 1 1 1 Compatibility With Other TMS320 CPUs The C28x DSP features compatibility modes that minimize the migration effort from the C27x and C2xLP CPUs The operating mode of the device is determined...

Page 21: ...ount compatible with the C27x CPU For detailed information on operating in C27x object compatible mode and migrating from the C27x see Appendix F 1 1 2 Switching to C28x Mode From Reset At reset the C...

Page 22: ...rupts The CPU does not contain memory a clock generator or peripheral devices For information about interfacing to these items see the C28x Peripheral User s Guide literature number SPRU566 and the da...

Page 23: ...e unsigned number 1 2 2 Emulation Logic The emulation logic includes the following features For more details about these features see Chapter 7 Emulation Features Debug and test direct memory access D...

Page 24: ...accesses and differentiate between accesses of different sizes 16 bit or 32 bit Clock and control signals These provide clocking for the CPU and the emulation logic and they are used to control and m...

Page 25: ...to as M0 and M1 Each of these blocks is 1K words in size M0 is mapped at addresses 00 000016 00 03FF16 and M1 is mapped at ad dresses 00 040016 00 07FF16 Like all other memory blocks on the C28x de v...

Page 26: ...Memory or Peripherals Reserved Reset Block M1 1 K 16 Vectors in RAM M0 VMAP 0 Block M0 1 K 16 SP 0000 3FF 400 7FF 3F 0000 FFFF FFFF 1000 9FF 800 Memory or Peripherals Reserved 3F FFFF A000 Low 64K C2x...

Page 27: ...cess the least significant byte LSByte or most significant byte MSByte of an ad dressed word Strobe signals indicate when such an access is occurring on a data bus 1 4 1 Address and Data Buses The mem...

Page 28: ...write and a data space write cannot happen simultaneously because both use the DWDB Transactions that use different buses can happen simultaneously For exam ple the CPU can read from program space usi...

Page 29: ...ch is read from program space For the read from program space the CPU places the program space source address on the program address bus PAB sets the appropri ate program space select signals and read...

Page 30: ...1 12...

Page 31: ...c multiply and shift operations When performing signed math the CPU uses 2s complement notation This chapter describes the architecture regis ters and primary functions of the CPU Topic Page 2 1 CPU A...

Page 32: ...hed from data memory For a data read it places the address on the data read address bus DRAB for a data write it loads the data write address bus DWAB The ARAU also increments or decrements the stack...

Page 33: ...1 Program address bus PAB 0 21 RESULT BUS Data read address bus DRAB 0 31 Data read data bus DRDB 0 31 Data read buffer register Multiplier barrel shifter and ALU Data program write data bus DWDB 0 31...

Page 34: ...0x00000000 XAR1 32 bits Auxiliary register 1 0x00000000 XAR2 32 bits Auxiliary register 2 0x00000000 XAR3 32 bits Auxiliary register 3 0x00000000 XAR4 32 bits Auxiliary register 4 0x00000000 XAR5 32...

Page 35: ...disabled P 32 bits Product register 0x00000000 PH 16 bits High half of P 0x0000 PL 16 bits Low half of P 0x0000 PC 22 bits Program counter 0x3F FFC0 RPC 22 bits Return program counter 0x00000000 SP 16...

Page 36: ...6 TL 16 PL 16 AL 16 AH 16 XT 32 P 32 ACC 32 A 6 bit offset is used when operating in C28x mode or C27x object compatible mode A 7 bit offset is used when operating in C2xLP source compatible mode The...

Page 37: ...byte or least significant byte of AH or AL This enables efficient byte pack ing and unpacking Figure 2 3 Individually Accessible Portions of the Accumulator ACC AH AL AH MSB AH ACC 31 16 AH MSB ACC 3...

Page 38: ...TL register This register can be loaded with a signed 16 bit value that is automatically sign ex tended to fill the 32 bit XT register The upper 16 bit portion of the XT register is referred to as the...

Page 39: ...Individually Accessible Halves of the P Register P PH P 31 16 PL P 15 0 When some instructions access P PH or PL all 32 bits are copied to the ALU shifter block where the barrel shifter may perform a...

Page 40: ...4 Data Page Pointer DP In the direct addressing modes data memory is addressed in blocks of 64 words called data pages The lower 4M words of data memory consists of 65 536 data pages labeled 0 through...

Page 41: ...FFC0 003F FFFF Data memory above 4M words is not accessible using the DP When operating in C2xLP source compatible mode a 7 bit offset is used and the least significant bit of the DP register is igno...

Page 42: ...that read or write to an even address For example if the SP contains the odd address 0000 008316 a 32 bit read operation reads from addresses 0000 008216 and 0000 008316 The SP overflows if its value...

Page 43: ...for information on the behavior of particular instructions AR0H AR7H are accessed only as part of XAR0 XAR7 and are not individually ac cessible Figure 2 8 XAR0 XAR7 Registers XARn 31 0 ARnH XARn 31 1...

Page 44: ...rs ST0 ST1 The C28x has two status registers ST0 and ST1 which contain various flag bits and control bits These registers can be stored into and loaded from data memory enabling the status of the mach...

Page 45: ...corresponding bit in the IER The DBGIER indicates the time critical interrupts that will be serviced if enabled while the DSP is in real time emulation mode and the CPU is halted The C28x CPU interrup...

Page 46: ...ls ACC with a positive or negative saturation value see the description for OVM on page 2 32 When ACC overflows in the positive direction from 7FFF FFFF16 to 8000 000016 the OVC is incremented by 1 Wh...

Page 47: ...ADD loc16 16bitSigned ADDB ACC 8bit ADDCL ACC loc32 ADDCU ACC loc16 ADDL ACC loc32 ADDL loc32 ACC ADDU ACC loc16 DMAC ACC P loc32 XAR7 INC loc16 MAC P loc16 XAR7 MAC P loc16 0 pma MOVA T loc16 MOVAD T...

Page 48: ...B ACC loc16 T SUBB ACC 8bit SUBBL ACC loc32 SUBL ACC loc32 SUBL loc32 ACC SUBRL loc32 ACC SUBU ACC loc16 SUBUL ACC loc32 SUBUL P loc32 Unsigned Instructions Effect on OVC OVCU ADDUL ACC loc32 Inc OVC...

Page 49: ...as follows 000 Left shift by 1 During the shift the low order bit is zero filled At reset this mode is selected 001 No shift 010 Right shift by 1 During the shift the lower bits are lost and the shif...

Page 50: ...XT sign loc32 uns PM MAC P loc16 XAR7 ACC ACC P PM MAC P loc16 0 pma ACC ACC P PM MOV loc16 P loc16 low P PM MOVA T loc16 ACC ACC P PM MOVAD T loc16 ACC ACC P PM MOVH loc16 P loc16 high P PM MOVP T l...

Page 51: ...r 800016 to 7FFF16 The instructions CMP CMPB and CMPL do not affect the state of the V flag Table 2 6 lists the instructions that are affected by V flag See Chapter 6 for more details on instructions...

Page 52: ...low MAC P loc16 XAR7 V 1 on signed overflow MAC P loc16 0 pma V 1 on signed overflow MAX AX loc16 if AX loc16 0 V 1 MAXL ACC loc32 if ACC loc32 0 V 1 MIN AX loc16 if AX loc16 0 V 1 MINL ACC loc32 if A...

Page 53: ...oc16 V 1 on signed overflow SUB ACC 16bit shift V 1 on signed overflow SUB ACC loc16 shift V 1 on signed overflow SUB ACC loc16 T V 1 on signed overflow SUB AX loc16 V 1 on signed overflow SUB loc16 A...

Page 54: ...Otherwise the instruction clears N As shown in Table 2 7 under overflow conditions the way the N flag is set for compare operations is different from the way it is set for addition or subtraction ope...

Page 55: ...6 the ADD instruction can set C but cannot clear C During subtractions decrements compares C is cleared if the subtraction generates a carry otherwise C is set There is one exception if you are using...

Page 56: ...carry else C 0 ADDCU ACC loc16 ACC ACC loc16 C C 1 on carry else C 0 ADDL ACC loc32 C 1 on carry else C 0 ADDL loc32 ACC C 1 on carry else C 0 ADDU ACC loc16 C 1 on carry else C 0 ADDUL ACC loc32 C 1...

Page 57: ...C 1 DMAC ACC P loc32 XAR7 C 1 on carry else C 0 IMACL P loc32 XAR7 C 1 on carry else C 0 IMPYAL P XT loc32 C 1 on carry else C 0 IMPYSL P XT loc32 C 0 on borrow else C 1 INC loc16 C 1 on carry else C...

Page 58: ...C 1 MIN AX loc16 for AX loc16 C 0 on borrow else C 1 MINL ACC loc32 for ACC loc32 C 0 on borrow else C 1 MOV loc16 AX COND C bit used as test condition MOVA T loc16 C 1 on carry else C 0 MOVAD T loc16...

Page 59: ...AT ACC C 0 SAT64 ACC P C 0 SB 8bitOff COND C bit used as test condition SBBU ACC loc16 ACC ACC loc16 C C 0 on borrow else C 1 SETC C C 1 SFR ACC 1 16 C ACC bit shift 1 SFR ACC T if T 0 C 0 else C ACC...

Page 60: ...carry else C 0 XMACD P loc16 pma C 1 on carry else C 0 XRETC COND C bit used as test condition TC Bit 2 Test control flag This bit shows the result of a test performed by either the TBIT test bit inst...

Page 61: ...AX COND TC bit used as test condition MOVB loc16 8bit COND TC bit used as test condition MOVL loc32 ACC COND TC bit used as test condition NEGTC ACC TC bit used as test condition NORM ACC XARn NORM A...

Page 62: ...s cleared SXM Bit 0 Sign extension mode bit SXM affects the MOV ADD and SUB instructions that use a 16 bit value in an operation on the 32 bit accumulator When the 16 bit value is loaded into MOV adde...

Page 63: ...C loc16 shift Affected By SXM ADD ACC loc16 T Affected By SXM CLRC SXM SXM 0 MOV ACC 16bit shift Affected By SXM MOV ACC loc16 shift Affected By SXM MOV ACC loc16 T Affected By SXM SETC SXM SXM 1 SFR...

Page 64: ...gister 000 XAR0 selected at reset 001 XAR1 010 XAR2 011 XAR3 100 XAR4 101 XAR5 110 XAR6 111 XAR7 XF Bit 12 XF status bit This bit reflects the current state of the XFS output signal which is com patib...

Page 65: ...cleared by any one of the following events An interrupt is serviced An interrupt is not serviced but takes the CPU out of the IDLE state A valid instruction enters the instruction register the registe...

Page 66: ...set vector are mapped to the lowest or highest addresses in program memory 0 CPU interrupt vectors are mapped to the bottom of program memory addresses 00 000016 00 003F16 1 CPU interrupt vectors are...

Page 67: ...GM is primarily used in emulation to block debug events in time critical portions of program code DBGM enables or disables debug events as follows 0 Debug events are enabled 1 Debug events are disable...

Page 68: ...Upon return from the interrupt INTM is restored from the stack This bit can be individually set and cleared by the SETC INTM instruction and CLRC INTM instruction respectively At reset INTM is set Th...

Page 69: ...rns break the sequential flow of instructions by trans ferring control to another location in program memory A branch only transfers control to the new location A call also saves the return address th...

Page 70: ...ch queue which holds instructions in preparation for decoding and execution The instruction fetch mechanism fetches 32 bits at a time from program memory it fetches one 32 bit instruction or two 16 bi...

Page 71: ...r before you execute the instruction Howev er the MAC and some versions of the MPY and MPYA instructions load T for you before the multiplication The other input is from one of the following J A data...

Page 72: ...the following J A program memory location Some C28x 32 X 32 multiply MAC type instructions such as IMACL and QMACL take one data value directly from memory using the program address bus J The 32 bit m...

Page 73: ...ication instruc tions can be combined to implement 32 X 32 64 bit or 64 X 64 128 bit math Figure 2 13 Conceptual Diagram of Components Involved in 32 X 32 Bit Multiplication XT Multiplier MUX From dat...

Page 74: ...ue are zero filled If the value has 16 bits and sign extension is specified the bits to the left are filled with copies of the sign bit If the value has 16 bits and sign extension is not specified the...

Page 75: ...SXM Store 16 LSBs of left shifted ACC Syntax MOV loc16 ACC 1 8 Shift left 0 ACC 16 LSBs to ALU Discard Store 16 MSBs of left shifted ACC Syntax MOVH loc16 ACC 1 8 Note This instruction performs a sing...

Page 76: ...s cleared Shift right ACC 32 bits to ACC 0 Sign SXM C Last bit out Discard other bits Logical right shift of AH or AL The last bit to be shifted out fills the carry bit C Syntaxes LSR AX shift LSR AX...

Page 77: ...shift T 5 0 Shift right ACC P 64 bits to ACC P 0 C Last bit out Discard other bits Logical left shift of ACC P Syntaxes LSL64 ACC P 1 16 LSL64 ACC P T shift T 5 0 Shift left 0 ACC P 64 bits to ACC P C...

Page 78: ...t of P as per PM bits Syntaxes ADD ACC P SUB ACC P CMP ACC P MAC P loc 0 pmem MOV ACC P MOVA T loc MOVP T loc MOVS T loc MPYA P loc 16BitSigned MPYA P T loc MPYS P T loc Shift left 0 P 32 bits to ALU...

Page 79: ...ht P Discard Sign Discard 16 LSBs to ALU For PM 0 For PM from 2 7 For PM 1 No shift Store 16 MSBs of shifted P P is shifted as per the PM bits The result is shifted right by 16 so that its 16 MSBs are...

Page 80: ...This page intentionally left blank 2 50 This page intentionally left blank...

Page 81: ...rolled through software Finally it describes how a hardware reset affects the CPU Topic Page 3 1 CPU Interrupts Overview 3 2 3 2 CPU Interrupt Vectors and Priorities 3 4 3 3 Maskable Interrupts INT1 I...

Page 82: ...h of the C28x interrupts whether hardware or software can be placed in one of the following two categories Maskable interrupts These are interrupts that can be blocked masked or enabled unmasked throu...

Page 83: ...odule the vector fetched will depend on the setting of the PIE enable and flag registers 4 Execute the interrupt service routine The C28x branches to its corre sponding subroutine called an interrupt...

Page 84: ...cimal form The table also shows the priority of each of the hardware interrupts Table 3 1 Interrupt Vectors and Priorities Absolute Address hexadecimal Hardware Vector VMAP 0 VMAP 1 Hardware Priority...

Page 85: ...ed software interrupt USER7 00 0034 3F FFF4 User defined software interrupt USER8 00 0036 3F FFF6 User defined software interrupt USER9 00 0038 3F FFF8 User defined software interrupt USER10 00 003A 3...

Page 86: ...ts To enable one of the interrupts in the IER you set the corresponding bit in the IER to enable the same interrupt in the DBGIER you set the corre sponding bit in the DBGIER The DBGIER indicates whic...

Page 87: ...waiting for ap proval from the CPU the corresponding IFR bit is 1 otherwise the IFR bit is 0 To identify pending interrupts use the PUSH IFR instruction and then test the value on the stack Use the O...

Page 88: ...ure 3 2 shows the IER To enable an interrupt set its corresponding bit to 1 To disable an interrupt clear its corresponding bit to 0 Two syntaxes of the MOV instruction allow you to read from the IER...

Page 89: ...TOSINT and DLOGINT RTOSINT Real time operating system interrupt enable bit Bit 15 RTOSINT 0 RTOSINT is disabled RTOSINT 1 RTOSINT is enabled DLOGINT Data log interrupt enable bit Bit 14 DLOGINT 0 DLOG...

Page 90: ...NT14 INT13 INT12 INT11 INT10 INT9 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 7 6 5 4 3 2 1 0 INT8 INT7 INT6 INT5 INT4 INT3 INT2 INT1 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 Note R Read ac...

Page 91: ...7 9 contains information on handling interrupts when the DSP is in real time mode and the CPU is halted When more than one interrupt is requested at the same time the C28x services them one after ano...

Page 92: ...M bit Clear corresponding IFR bit Yes No Clear corresponding IER bit Set INTM and DBGM Clear LOOP EALLOW and IDLESTAT Execute interrupt service routine Program continues Increment and temporarily stor...

Page 93: ...the CPU no other interrupts can be serviced until the CPU has begun executing the in terrupt service routine for the approved interrupt step 13 The IER is de scribed in section 3 3 2 ST1 is described...

Page 94: ...e menting SP by 1 ensures that the first 32 bit access does not overwrite the previous stack value 9 Perform automatic context save A number of register values are saved automatically to the stack The...

Page 95: ...and DBGM Clear LOOP EALLOW and IDLESTAT All these bits are in status register ST1 By setting INTM to 1 the CPU prevents maskable interrupts from disturbing the ISR If you wish to nest interrupts have...

Page 96: ...ram continues If the interrupt is not approved by the CPU the inter rupt is ignored and the program continues uninterrupted If the interrupt is approved its interrupt service routine is executed and t...

Page 97: ...an execute the interrupt service routine for INT1 by using the following instruction INTR INT1 Once an interrupt is initiated by the INTR instruction how it is handled depends on which interrupt is sp...

Page 98: ...or an interrupt initiated by the TRAP instruction For more details about the TRAP instruction see Chapter6 C28x Assembly Language Instruc tions Note The TRAP 0 instruction does not initiate a full res...

Page 99: ...k 4 Fetch interrupt vector The PC is set to point to the appropriate vector location based on the VMAP bit and the interrupt and the vector located at the PC address is loaded into the PC To determine...

Page 100: ...SP position after save All registers are saved as pairs as shown The P register is saved with 0 shift CPU ignores current state of the product shift mode bits PM in status register 0 The DBGSTAT regis...

Page 101: ...nowl edge signal The IACK instruction accepts a 16 bit constant as an operand and drives this 16 bit value on the 16 least significant lines of the data write bus DWDB 15 0 For a detailed description...

Page 102: ...onds to the ITRAP1 instruction An illegal instruction trap cannot be blocked not even during emulation Once initiated an illegal instruction trap operates the same as a TRAP 19 instruc tion The handli...

Page 103: ...S cannot be masked there are some debug execution states in which RS is not serviced see section 7 4 Execution Control Modes on page 7 7 Table 3 5 Registers After Reset Register Bit s Value After Rese...

Page 104: ...or at program space address 00 000016 or 3F FFC016 RPC all 000016 SP all SP 0x400 SP points to address 0400 ST0 0 SXM 0 Sign extension is suppressed 1 OVM 0 Overflow mode is off 2 TC 0 3 C 0 4 Z 0 5 N...

Page 105: ...accesses and events are disabled 2 PAGE0 0 PAGE0 stack addressing mode is enabled PAGE0 direct addressing mode is disabled 3 VMAP 1 The interrupt vectors are mapped to program memory addresses 3F FFC...

Page 106: ...fter Reset Continued Register Bit s Value After Reset Comments 12 XF 0 XFS output signal is low 13 15 ARP 0002 ARP points to AR0 XT all 0000 000032 Note The registers listed in this table are introduc...

Page 107: ...ation of the pipeline In addition you should be aware of two types of pipeline con flicts the pipeline does not protect against and how you can avoid them see section 4 5 For more information about th...

Page 108: ...hase of completion Following are descriptions of the eight phases in the order they occur The address and data buses mentioned in these descriptions are introduced in section 1 4 1 on page 1 9 Fetch 1...

Page 109: ...ta was addressed in the R1 phase the read 2 R2 hardware fetches that data by way of the appropriate data bus es Execute E In the execute E phase the CPU performs all multiplier shifter and ALU operati...

Page 110: ...ew instructions is delayed Events that cause portions of the pipeline to halt are described in section 4 3 Instructions in their fetch 1 fetch 2 and decode 1 phases are discarded if an interrupt or ot...

Page 111: ...bit or 32 bit it fills the instruction counter IC with the ad dress of the next instruction to undergo D2 decoding On an interrupt or call operation the IC value represents the return address which i...

Page 112: ...5916 00 005B16 00 005D16 00 005C16 00 005A16 00 005816 00 005616 00 005416 00 005216 00 005016 I C Instruction 2 Instruction 3 Instruction fetch queue 32 bits wide Instruction register 32 bits wide In...

Page 113: ...he diagram shows results being written to the low half of the accumulator AL In the W column address and a data values are driven simultaneously on the appropriate memory buses For example in the last...

Page 114: ...00 0204 00 0045 F34A I6 ADD AL XAR0 Add content of VarB 1 VarD address 00 0205 to AL and add 1 to XAR0 00 0046 F34B I7 MOV VarD AL Replace content of VarD with content of AL 00 0047 F34C I8 ADD AL XA...

Page 115: ...peline is full there is an instruction in every pipeline phase Also the effective execution time for each of these instructions is one cycle Some instructions finish their activity at the D2 phase som...

Page 116: ...cause the F1 D1 hardware and the D2 W hardware are decoupled instructions that are in their D2 W phases continue to execute Wait states in the R1 phase All D2 W activities of the pipeline freeze This...

Page 117: ...d by 32 bit fetches at subsequent even addresses Thus if the first instruction after a discontinuity is at an odd address and has 32 bits two fetches are required to get the entire instruction The D2...

Page 118: ...the Same Data Space Location Consider two instructions A and B Instruction A writes a value to a memory location during its W phase Instruction B must read that value from the same location during it...

Page 119: ...LRC instruction between I1 and I2 reduces the number of pipe line protection cycles to two Inserting two more instructions would remove the need for pipeline protection As a general rule if a read ope...

Page 120: ...R0 7 Load AR0 with the value addressed by the operand 7 and clear the upper half of XAR0 I2 MOV AH XAR0 Load AH with the value pointed to by XAR0 D2 R1 R2 E W Cycle I1 1 I2 I1 2 I2 I1 3 I2 I1 4 I2 I1...

Page 121: ...15 Pipeline need for pipeline protection As a general rule if a read operation occurs within three instructions from a write operation to the same register the pipeline protection mechanism adds at le...

Page 122: ...a1 PREAD AR1 XAR7 Load AR1 from program memory location given by XAR7 The operands Data1 and XAR7 are referencing the same location but the pipeline cannot interpret this fact The PREAD instruction re...

Page 123: ...sure that any read operation that follows a write operation within a protected address range is executed as written by delaying the read operation until the write is initiated See your device data she...

Page 124: ...d protected_area Example 2 write protected_area write protected_area write protected_area no pipe protection invoked read non_protected_area pipe protection 2 cycles read protected_area read protected...

Page 125: ...DE 5 4 5 3 Assembler Compiler Tracking of AMODE Bit 5 7 5 4 Direct Addressing Modes DP 5 8 5 5 Stack Addressing Modes SP 5 9 5 6 Indirect Addressing Modes 5 10 5 7 Register Addressing Modes 5 25 5 8 D...

Page 126: ...e for accessing data on the stack or the stack pointer can be post incremented or pre decremented when pushing and popping data from the stack respectively Indirect Addressing Mode XAR0 to XAR7 auxili...

Page 127: ...are Data Program IO Space Immediate Addressing Modes In this mode the address of the memory operand is embedded in the in struction Program Space Indirect Addressing Modes Some instructions can access...

Page 128: ...ode contains addressing modes that are fully compatible to the C2xLP device The data page pointer offset is increased to 7 bits and all of the indirect addressing modes available on the C2xLP are supp...

Page 129: ...1 0 110 RRR 0 0 BR0 BR0 ARPn 1 0 111 000 1 0 111 001 1 0 111 010 1 0 111 011 1 0 111 100 1 0 101 110 1 0 101 111 1 0 110 RRR 1 1 000 RRR 1 1 001 RRR 1 1 010 RRR 1 1 011 RRR 1 1 100 RRR 1 1 101 RRR 0...

Page 130: ...is currently used and which pointer is used in the next operation The examples below illustrate the differences between the C28x Indirect and C2xLP Indirect addressing modes ADD AL XAR4 Read the cont...

Page 131: ...erride the default mode and change syntax check ing to the new address mode setting c28_amode Tells assembler that any code that follows assumes AMODE 0 C28x addressing modes lp_amode Tells assembler...

Page 132: ...A B AMODE loc16 loc32 Syntax Description 1 7bit 32bitDataAddr 31 22 0 32bitDataAddr 21 7 DP 15 1 32bitDataAddr 6 0 7bit Note The 7 bit offset value is concatenated with the upper 15 bits of the DP reg...

Page 133: ...m stack location 12 words from top of stack to ACC register MOVL SP 34 ACC Store 32 bit ACC register to stack location 34 words from top of stack AMODE loc16 loc32 Syntax Description X SP 32bitDataAdd...

Page 134: ...op count N Loop MOVL ACC XAR2 Load ACC with location pointed to by XAR2 post increment XAR2 MOVL XAR3 ACC Store ACC into location pointed to by XAR3 post increment XAR3 BANZ Loop AR0 Loop until AR0 0...

Page 135: ...to the selected 32 bit register Upper 16 bits of XAR0 are ignored AR0 is treated as an unsigned 16 bit value Overflow into the upper 16 bits of XARn can occur Example s MOVW DP Array1Ptr Point to Arra...

Page 136: ...of data memory space NOP ARP2 Set ARP pointer to point to XAR2 MOV 0x0404 Store 0x0404 into location pointed by XAR2 NOP ARP3 Set ARP pointer to point to XAR3 MOV 0x8000 Store 0x8000 into location poi...

Page 137: ...RP0 Set ARP pointer to point to XAR0 XBANZ Loop Loop until AR0 0 post decrement AR0 AMODE loc16 loc32 Syntax Description X ARPn 32bitDataAddr 31 0 XAR ARP if loc16 XAR ARP XAR ARP 1 if loc32 XAR ARP X...

Page 138: ...RP pointer to point to XAR0 XBANZ Loop Loop until AR0 0 post decrement AR0 AMODE loc16 loc32 Syntax Description 1 ARPn 32bitDataAddr 31 0 XAR ARP if loc16 XAR ARP XAR ARP 1 if loc32 XAR ARP XAR ARP 2...

Page 139: ...ARP pointer to point to XAR1 XBANZ Loop Loop until AR1 0 post decrement AR1 AMODE loc16 loc32 Syntax Description 1 0 ARPn 32bitDataAddr 31 0 XAR ARP XAR ARP XAR ARP AR0 ARP n Note The lower 16 bits o...

Page 140: ...r to point to XAR1 XBANZ Loop Loop until AR1 0 post decrement AR1 AMODE loc16 loc32 Syntax Description 1 0 ARPn 32bitDataAddr 31 0 XAR ARP XAR ARP XAR ARP AR0 ARP n Note The lower 16 bits of XAR0 are...

Page 141: ...R0 ACC Store ACC into location pointed to by XAR3 post increment XAR3 with AR0 reverse carry add NOP ARP1 Set ARP pointer to point to XAR1 XBANZ Loop Loop until AR1 0 post decrement AR1 AMODE loc16 lo...

Page 142: ...R0 ignored Up per 16 bits of the selected register unchanged by the operation Example s Transfer contents of Array1 to Array2 in bit reverse order MOVL XAR2 Array1 N 1 2 Load XAR2 with end address of...

Page 143: ...2 Array1 N 1 2 Load XAR2 with end address of Array1 MOVL XAR3 Array2 N 1 2 Load XAR3 with end address of Array2 MOV AR0 N Load AR0 with size of array N must be a multiple of 2 2 4 8 16 MOV AR1 N 1 Loa...

Page 144: ...00 1000 XAR ARP 15 0 0000 0000 0000 0100 AR0 0000 0000 0000 1000 XAR ARP 15 0 0000 0000 0000 1100 AR0 0000 0000 0000 1000 XAR ARP 15 0 0000 0000 0000 0010 AR0 0000 0000 0000 1000 XAR ARP 15 0 0000 000...

Page 145: ...16 unchanged ARP 6 As seen in Figure 5 1 buffer size is determined by the 8 LSBs of AR1 or AR1 7 0 Specifically the buffer size is AR1 7 0 1 When AR1 7 0 is 255 then the buffer size is at its maximum...

Page 146: ...filter X N data array C N coefficient array MOVW DP Xpointer Load DP with page address of Xpointer MOVL XAR6 Xpointer Load XAR6 with current X pointer MOVL XAR7 C Load XAR7 with start address of C arr...

Page 147: ...6 Note With this addressing mode there is no circular buffer alignment require ments As seen in Figure 5 2 buffer size is determined by the upper 16 bits of XAR1 or XAR1 31 16 Specifically the size i...

Page 148: ...N coefficientv array MOVW DP Xindex Load DP with page address of Xindex MOVL XAR6 X Load XAR6 with start address of X array MOV AH N Load AH with size of array X N MOV AL Xindex Load AL with current c...

Page 149: ...AR6 with contents of P MOVL P XT Load P with contents of XT register ADDL ACC P ACC ACC P AMODE loc32 Syntax Description X XT Access contents of 32 bit XT register Example s MOVL XAR6 XT Load XAR6 wit...

Page 150: ...Load T with contents of AL AMODE loc16 Syntax Description X AH Access contents of 16 bit AH register AL register contents are un affected When the AH register is the destination operand this may affe...

Page 151: ...V PL T Load PL with contents of T ADD AL T AL AL T MOVZ AR4 T Load AR4 with contents of T AR4H 0 AMODE loc16 Syntax Description X SP Access contents of 16 bit SP register Example s MOVZ AR4 SP Load AR...

Page 152: ...iate value Note If instruction is repeated the address is post incremented on each iteration The I O strobe signal is toggled when accessing I O space with this addressing mode The data space address...

Page 153: ...ue Note If instruction is repeated the address is post incremented on each iteration This addressing mode can only access the upper 64K of program space Instructions that use this addressing mode XPRE...

Page 154: ...ster is not modified For all other instructions the address is not incremented even when repeated Instructions that use this addressing mode MAC P loc16 XAR7 ACC ACC P PM P loc16 ProgSpace XAR7 DMAC A...

Page 155: ...taAddr 31 0 XARn Offset Offset AR0 AR1 3bit if Offset Even Value Access LSByte Of 16 bit Memory Location Leave MSByte untouched if Offset Odd Value Access MSByte Of 16 bit Memory Location Leave LSByte...

Page 156: ...LSB untouched AX MSB loc16 LSB if offset odd AX LSB untouched AX MSB loc16 MSB else AX LSB untouched AX MSB loc16 LSB MOVB loc16 AX LSB if address mode XARn AR0 AR1 3bit if offset even loc16 LSB AX L...

Page 157: ...t of the address generation unit does not force alignment hence pointer values retain their values For example MOVB AR0 5 AR0 5 MOVL AR0 ACC AL address 0x000004 AH address 0x000005 AR0 5 The programme...

Page 158: ...presents summaries of the instruction set defines special sym bols and notations used and describes each instruction in detail in alphabeti cal order Topic Page 6 1 Instruction Set Summary Organized b...

Page 159: ...register pointer ARP0 to ARP7 ARP0 points to XAR0 and ARP7 points to XAR7 AR ARP Lower 16 bits of auxiliary register pointed to by ARP XAR ARP Auxiliary registers pointed to by ARP AX Accumulator high...

Page 160: ...ended 16bit 16 bit immediate value 0 16bit 16 bit immediate value zero extended S 16bit 16 bit immediate value sign extended 22bit 22 bit immediate value 0 22bit 22 bit immediate value zero extended L...

Page 161: ...2 MOVB XARn 8bit Load auxiliary register with 8 bit value 6 200 MOVB AR6 7 8bit Load auxiliary register with an 8 bit constant 6 188 MOVL XARn loc32 Load 32 bit auxiliary register 6 214 MOVL loc32 XAR...

Page 162: ...276 POP ST0 Pop ST0 register from stack 6 277 POP ST1 Pop ST1 register from stack 6 278 POP T ST0 Pop T ST0 registers from stack 6 279 POP XT Pop XT register from stack 6 281 POP XARn Pop auxiliary re...

Page 163: ...oc16 16bit Bitwise AND 6 45 AND AX loc16 Bitwise AND 6 49 AND loc16 AX Bitwise AND 6 48 ANDB AX 8bit Bitwise AND 8 bit value 6 51 ASR AX 1 16 Arithmetic shift right 6 53 ASR AX T Arithmetic shift righ...

Page 164: ...4 SUB AX loc16 Subtract specified location from AX 6 338 SUB loc16 AX Subtract AX from specified location 6 339 SUBR loc16 AX Reverse subtract specified location from AX 6 354 SXTB AX Sign extend LSB...

Page 165: ...3 SUB ACC 16bit 0 15 Subtract shifted value from accumulator 6 337 SUBB ACC 8bit Subtract 8 bit value 6 340 SBBU ACC loc16 Subtract unsigned value plus inverse borrow 6 317 SUBU ACC loc16 Subtract uns...

Page 166: ...the 32 bit minimum 6 155 MOVL ACC loc32 Load accumulator with 32 bits 6 204 MOVL loc32 ACC Store 32 bit accumulator 6 206 MOVL P ACC Load P from the accumulator 6 212 MOVL ACC P PM Load the accumulato...

Page 167: ...Arithmetic shift right of 64 bit value by T 5 0 6 56 CMP64 ACC P Compare 64 bit value 6 77 LSL64 ACC P 1 16 Logical shift left 1 to 16 places 6 137 LSL64 ACC P T 64 bit logical shift left by T 5 0 6 1...

Page 168: ...16 Load the T register and store P in the accumulator 6 217 MOVS T loc16 Load T and subtract P from the accumulator 6 218 MOVX TL loc16 Load lower half of XT with sign extension 6 224 SUBUL P loc32 Su...

Page 169: ...ate lower half 6 100 IMPYAL P XT loc32 Signed 32 bit multiply lower half and add previous P 6 103 IMPYL P XT loc32 Signed 32 X 32 bit multiply lower half 6 106 IMPYL ACC XT loc32 Signed 32 X 32 bit mu...

Page 170: ...te conditionally 6 194 OR loc16 16bit Bitwise OR 6 262 TBIT loc16 bit Test bit 6 359 TBIT loc16 T Test bit specified by T register 6 360 TCLR loc16 bit Test and clear specified bit 6 361 TSET loc16 bi...

Page 171: ...ddr Long call using RPC 6 123 LCR XARn Long indirect call using RPC 6 124 LOOPZ loc16 16bit Loop while zero 6 127 LOOPNZ loc16 16bit Loop while not zero 6 125 LRET Long return 6 130 LRETE Long return...

Page 172: ...rupts 6 46 AND IFR 16bit Bitwise AND to clear pending CPU interrupts 6 47 IACK 16bit Interrupt acknowledge 6 97 INTR INT1 INT14 NMI EMUINT DLOGINT RTOSINT Emulate hardware interrupts 6 114 MOV IER loc...

Page 173: ...OVC Store the unsigned overflow counter 6 221 SETC Mode Set multiple status bits 6 320 SETC XF Set XF bit and output signal 6 324 SETC C28MAP M0M1MAP Set M0M1MAP bit Set the M0M1MAP bit 6 65 6 322 SE...

Page 174: ...perations 6 17 C28x Assembly Language Instructions Table 6 2 Register Operations Continued Mnemonic Page Description Miscellaneous Operations Continued ESTOP0 Emulation Stop 0 6 93 ESTOP1 Emulation St...

Page 175: ...n logic assumes that the original debug context will be restored The abort interrupt ABORTI instruction is provided as a means to indicate that the debug context will not be restored and the debug log...

Page 176: ...ACC 0x8000 0000 at the start of the operation this is considered an overflow value and V is set Otherwise V is not affected OVM If ACC 0x8000 0000 at the start of the operation this is considered an o...

Page 177: ...s cleared g Modes Z After the operation the Z flag is set if the ACC is zero else Z is cleared C The C flag bit is cleared V If ACC 0x8000 0000 at the start of the operation this is considered an over...

Page 178: ...abs value TC sign TC MOV T AH Temp save Den16 in T register MOV ACC Num16 16 AH Num16 AL 0 ABSTC ACC Take abs value TC sign TC MOVU ACC AH AH 0 AL Num16 RPT 15 Repeat operation 16 times SUBCU ACC T C...

Page 179: ...Modes Z After the addition the Z flag is set if the ACC value is zero else the flag is cleared N After the addition the N flag is set if bit 31 of the ACC is 1 else the flag is cleared C If the additi...

Page 180: ...ADD ACC 16bit 0 15 6 23 MOV ACC VarB 10 Load ACC with VarB left shifted by 10 ADD ACC 23 6 Add 23 left shifted by 6 to ACC...

Page 181: ...ddition generates a carry C is set otherwise C is cleared V If an overflow occurs V is set otherwise V is not affected OVC If OVM 0 disabled and the operation generates a positive overflow then the co...

Page 182: ...1 of the ACC is 1 else N is cleared C If the addition generates a carry C is set otherwise C is cleared Exception If a shift of 16 is used the ADD instruction can set C but not clear C V If an overflo...

Page 183: ...loc16 0 16 6 26 Example Calculate signed value ACC VarA 10 VarB 6 SETC SXM Turn sign extension mode on MOV ACC VarA 10 Load ACC with VarA left shifted by 10 ADD ACC VarB 6 Add VarB left shifted by 6...

Page 184: ...sted for a zero condition The zero flag bit is set if the operation results in AX 0 otherwise it is cleared C If the addition generates a carry C is set otherwise C is cleared V If an overflow occurs...

Page 185: ...tion loc16 is tested for a zero condition The zero flag bit is set if the operation generates loc16 0 otherwise it is cleared C If the addition generates a carry C is set otherwise C is cleared V If a...

Page 186: ...L or AH and 16bitSigned is an 8 bit number then the assembler will encode this instruction as ADDB AX 16bitSigned to improve efficiency To override this encoding use the ADDW loc16 16bitSigned instruc...

Page 187: ...occurs V is set otherwise V is not affected OVC If OVM 0 disabled then if the operation generates a positive overflow then the counter is incremented and if the operation generates a negative overflo...

Page 188: ...flag bit is set if the operation results in AX 0 otherwise it is cleared C If the addition generates a carry C is set otherwise C is cleared V If an overflow occurs V is set otherwise V is not affect...

Page 189: ...7 bit unsigned constant to SP and store the result in SP SP SP 0 7bit Flags and Modes None Repeat This instruction is not repeatable If this instruction follows the RPT instruction it resets the repea...

Page 190: ...scription Add a 7 bit unsigned constant to XARn and store the result in XARn XARn XARn 0 7bit Flags and Modes None Repeat This instruction is not repeatable If this instruction follows the RPT instruc...

Page 191: ...en if the operation generates a positive overflow then the counter is incremented and if the operation generates a negative overflow then the counter is decremented If OVM 1 enabled then the counter i...

Page 192: ...ise C is cleared V If an overflow occurs V is set otherwise V is not affected OVC If OVM 0 disabled then if the operation generates a positive overflow then the counter is incremented and if the opera...

Page 193: ...f OVM 0 disabled then if the operation generates a positive overflow then the counter is incremented and if the operation generates a negative overflow then the counter is decremented If OVM 1 enabled...

Page 194: ...egative overflow then the counter is decremented If OVM 1 enabled then the counter is not affected by the operation OVM If overflow mode bit is set then the ACC value will saturate maximum positive 0x...

Page 195: ...If the addition generates a carry C is set otherwise C is cleared V If an overflow occurs V is set otherwise V is not affected OVC If OVM 0 disabled then if the operation generates a positive overflo...

Page 196: ...ration generates a positive overflow then the counter is incremented and if the operation generates a negative overflow then the counter is decremented If OVM 1 enabled then the counter is not affecte...

Page 197: ...r is 1 then set the N flag otherwise clear N Z After the addition if the value of the P register is 0 then set the Z flag otherwise clear Z C If the addition generates a carry set C otherwise C is cle...

Page 198: ...he ACC is 1 else N is cleared C If the addition generates a carry C is set otherwise C is cleared V If an overflow occurs V is set otherwise V is not affected OVCU The overflow counter is incremented...

Page 199: ...uxiliary Register XAR0 to XAR7 This pointer determines which Auxiliary register is modified by the operation Repeat This instruction is not repeatable If this instruction follows the RPT instruction i...

Page 200: ...are zero filled before the AND operation The result is stored in the ACC register ACC ACC AND 0 16bit shift value Flags and Modes N The load to ACC is tested for a negative condition If bit 31 of ACC...

Page 201: ...e ACC register ACC ACC AND 0 loc16 Flags and N Clear flag g Modes Z The load to ACC is tested for a zero condition The zero flag bit is set if the operation generates ACC 0 otherwise it is cleared Rep...

Page 202: ...condition If bit 15 of AX is 1 then the negative flag bit is set otherwise it is cleared Z The load to AX is tested for a zero condition The zero flag bit is set if the operation generates AX 0 otherw...

Page 203: ...cription Disable specific interrupts by performing a bitwise AND operation with the IER register and the 16 bit immediate value The result is stored in the IER register IER IER AND 16bit Flags and Mod...

Page 204: ...ter and the 16 bit immediate value The result of the AND operation is stored in the IFR register IFR IFR AND 16bit Note Interrupt hardware has priority over CPU instruction operation in cases where th...

Page 205: ...16 loc16 AND AX This is a read modify write operation Flags and Modes N The load to loc16 is tested for a negative condition If bit 15 of loc16 is 1 then the negative flag bit is set otherwise it is c...

Page 206: ...AX AX AND 16bit Flags and Modes N The load to AX is tested for a negative condition If bit 15 of AX is 1 then the negative flag bit is set otherwise it is cleared Z The load to AX is tested for a zero...

Page 207: ...on pointed to by loc16 loc16 loc16 AND 16bit Smart Encoding If loc16 AH or AL and 16bitSigned is an 8 bit number then the assembler will encode this instruction as ANDB AX 8 bit to improve efficiency...

Page 208: ...s and Modes N The load to AX is tested for a negative condition If bit 15 of AX is 1 then the negative flag bit is set otherwise it is cleared Z The load to AX is tested for a zero condition The zero...

Page 209: ...lignment has taken place In either case the change to the SPA bit is made in the decode 2 phase of the pipeline if SP odd SP SP 1 SPA 1 else SPA 0 If you wish to undo a previous alignment by the ASP i...

Page 210: ...tatus flag bit SIGN C AX AX Discard other bits Right shift Immediate value Last bit out Flags and Modes N After the shift if bit 15 of AX is 1 then the negative flag bit is set otherwise it is cleared...

Page 211: ...d Modes N After the shift if bit 15 of AX is 1 then the negative flag bit is set otherwise it is cleared Even if the T 3 0 register bits specify a shift of 0 the value of AH or AL is still tested for...

Page 212: ...lags and Modes N After the shift if bit 31 of the ACC register is 1 then ACC P is negative and the N bit is set otherwise N is cleared Z After the shift the Z flag is set if the combined 64 bit value...

Page 213: ...out or cleared Discard other bits Flags and Modes N After the shift if bit 31 of the ACC register is 1 then ACC P is negative and the N bit is set otherwise N is cleared Z After the shift the Z flag...

Page 214: ...Modes Z After the shift the Z flag is set if the ACC value is zero else Z is cleared Even if the T register specifies a shift of 0 the content of the ACC register is still tested for the zero conditio...

Page 215: ...C 0 1001 LOS Lower Or Same C 0 OR Z 1 1010 NOV No Overflow V 0 1011 OV Overflow V 1 1100 NTC Test Bit Not Set TC 0 1101 TC Test Bit Set TC 1 1110 NBIO BIO Input Equal To Zero BIO 0 1111 UNC Unconditi...

Page 216: ...ary register is decremented by 1 The upper 16 bits of the auxiliary register ARnH is not used in the comparison and is not affected by the post decrement if ARn 0 PC PC signed 16 bit offset ARn ARn 1...

Page 217: ...ers ARn and ARm registers and branch if the specified condition is true otherwise continue execution without branching If tested condition true PC PC signed 16 bit offset If tested condition false PC...

Page 218: ...verflow V 1 1100 NTC Test Bit Not Set TC 0 1101 TC Test Bit Set TC 1 1110 NBIO BIO Input Equal To Zero BIO 0 1111 UNC Unconditional Description Fast conditional branch If the specified condition is tr...

Page 219: ...0 0400 00 07FF C27x Compatible Mapping M0M1MAP 0 M1 M0 M1 Program Space Data Space 00 0000 00 0400 00 07FF M0 M1 Note The pipeline is flushed when this instruction is executed Flags and Modes M0M1M AP...

Page 220: ...default mode of the processor after reset Note The pipeline is flushed when this instruction is executed Flags and Modes Clear the OBJMODE bit Repeat This instruction is not repeatable If this instru...

Page 221: ...ine Flags and Modes AMODE The AMODE bit is cleared Repeat This instruction is not repeatable If this instruction follows the RPT instruction it resets the repeat counter RPTC and executes only once Ex...

Page 222: ...Data Space 00 0000 00 0400 00 07FF C27x Compatible Mapping M0M1MAP 0 M1 M0 M1 Program Space Data Space 00 0000 00 0400 00 07FF M0 M1 Note The pipeline is flushed when this instruction is executed Flag...

Page 223: ...object mode supports C2xLP source Flags and Modes OBJ MODE Set the OBJMODE bit Repeat This instruction is not repeatable If this instruction follows the RPT instruction it resets the repeat counter R...

Page 224: ...it is cleared Repeat This instruction is not repeatable If this instruction follows the RPT instruction it resets the repeat counter RPTC and executes only once Example Execute the operation VarC VarA...

Page 225: ...ing M0M1MAP 0 M1 M0 M1 Program Space Data Space 00 0000 00 0400 00 07FF M0 M1 Note The pipeline is flushed when this instruction is executed This bit is provided for compatibility for users migrating...

Page 226: ...instruction is executed Flags and Modes OBJ MODE The OBJMODE bit is cleared Repeat This instruction is not repeatable If this instruction follows the RPT instruction it resets the repeat counter RPTC...

Page 227: ...ow counter OVC bits in ST0 Flags and Modes OVC The 6 bit overflow counter bits OVC are cleared Repeat This instruction is not repeatable If this instruction follows the RPT instruction it resets the r...

Page 228: ...sponding output signal low Flags and Modes XF The XF status bit is cleared Repeat This instruction is not repeatable If this instruction follows the RPT instruction it resets the repeat counter RPTC a...

Page 229: ...Description Clear the specified status bits The mode operand is a mask value that relates to the status bits in this way Mode bit Status Register Flag Cycles 0 ST0 SXM 1 1 ST0 OVM 1 2 ST0 TC 1 3 ST0 C...

Page 230: ...gs SETC INTM DBGM Set INTM and DBGM bits to 1 CLRC TC C SXM OVM Clear TC C SXM OVM bits to 0 CLRC 0xFF Clear all bits to 0 SETC 0xFF Set all bits to 1 SETC C SXM TC OVM Set TC C SXM OVM bits to 1 CLRC...

Page 231: ...ecision when it determines the sign of the result For example consider the subtraction 0x8000 0x0001 If the precision were limited to 16 bits the result would cause an overflow to the positive number...

Page 232: ...set otherwise it is cleared The CMP instruction assumes infinite precision when it deter mines the sign of the result For example consider the subtraction 0x8000 0x0001 If the precision were limited t...

Page 233: ...CMP loc16 16bit 6 76 Example Calculate if VarA 20 VarA 0 CMP VarA 20 Set flags on VarA 20 MOVB VarA 0 GT Zero VarA if greater then...

Page 234: ...instruction takes into account the state of the overflow flag V to increase precision when determining if ACC is negative For example consider the subtraction on ACC of 0x8000 0000 0x0000 0001 This re...

Page 235: ...VarA 0 Load P with low 32 bits of VarA MOVL ACC VarA 2 Load ACC with high 32 bits of VarA SUBUL P VarB 0 Sub from P unsigned low 32 bits of VarB SUBBL ACC VarB 2 Sub from ACC with borrow high 32 bits...

Page 236: ...subtraction 0x8000 0x0001 If the precision were limited to 16 bits the result would cause an overflow to the positive number 0x7FFF and N would be cleared However because the CMPB instruction assumes...

Page 237: ...ider the subtraction 0x8000 0000 0x0000 0001 If the precision were limited to 32 bits the result would cause an overflow to the positive number 0x7FFF FFFF and N would be cleared However because the C...

Page 238: ...n overflow to the positive number 0x7FFF FFFF and N would be cleared However because the CMPL instruction assumes infinite precision it would set N to indicate that 0x8000 0000 0x0000 0001 actually re...

Page 239: ...3 if AR0 AR ARP TC 1 else TC 0 Flags and Modes ARP The 3 bit ARP points to the current valid Auxiliary Register XAR0 to XAR7 This pointer determines which Auxiliary register is compared to AR0 TC If t...

Page 240: ...algorithms such as calculating Square Root of a number calculating the inverse of a number searching for the first 1 bit in a word Flags and Modes N N is set if bit 31 of ACC is 1 else N is cleared Z...

Page 241: ...N After the operation if bit 15 of loc16 is 1 set N otherwise clear N Modes Z After the operation if loc16 is zero set Z otherwise clear Z C If the subtraction generates a borrow C is cleared otherwi...

Page 242: ...M status bit DINT has no effect on the unmaskable reset or NMI interrupts Flags and Modes INTM The instruction sets this bit to disable interrupts Repeat This instruction is not repeatable If this ins...

Page 243: ...e between the upper words of the 32 bit locations pointed to by the loc32 and XAR7 addressing modes and second multiplication takes place with the lower words Temp XT 16 bits VarB_1 VarB_2 XAR7 VarA_1...

Page 244: ...counter is incremented If overflow mode is disabled and if the operation generates a negative overflow of the ACC register then the counter is decremented OVM If overflow mode bit is set then the ACC...

Page 245: ...must be aligned to even address N must be an even number sum 0 for i 0 i N i sum sum X i C i 5 MOVL XAR2 X XAR2 pointer to X MOVL XAR7 C XAR7 pointer to C SPM 5 Set product shift to 5 ZAPA Zero ACC P...

Page 246: ...y loc16 into the next highest address loc16 1 loc16 Flags and Modes None Repeat This instruction is repeatable If the operation is follows a RPT instruction then it will be executed N 1 times Example...

Page 247: ...n an interrupt or trap the current state of the EALLOW bit is saved off onto the stack within ST1 and the EALLOW bit is autocratically cleared Therefore at the start of an interrupt service routine ac...

Page 248: ...rticular device to determine which registers the EALLOW bit protects To allow write access to the registers use the EALLOW instruction Flags and Modes EALLOW The EALLOW flag is cleared Repeat This ins...

Page 249: ...y clearing the INTM status bit Flags and Modes INTM This bit is cleared by the instruction to enable interrupts Repeat This instruction is not repeatable If this instruction follows the RPT instructio...

Page 250: ...is instruction causes the C28x to halt regardless of the state of the DBGM bit in status register ST1 In addition ESTOP0 does not increment the PC When an emulator is not connected or when a debug pro...

Page 251: ...x to halt regardless of the state of the DBGM bit in status register ST1 Before halting the processor ESTOP1 increments the PC so that it points to the instruction following the ESTOP1 When an emulato...

Page 252: ...call The return PC value is stored into the XAR7 register and the 22 bit immediate destination address is loaded into the PC XAR7 21 0 PC 2 XAR7 31 22 0 PC 22 bit Flags and Modes None Repeat This inst...

Page 253: ...N After the operation if bit 15 of AX is 1 then the negative flag bit is set other wise it is cleared Z After the operation if AX is 0 then the Z bit is set otherwise it is cleared Repeat This instruc...

Page 254: ...wledge an interrupt by outputting the specified 16 bit constant on the low 16 bits of the data bus Certain peripherals will provide the capability to capture this value to provide low cost trace See t...

Page 255: ...the CPU enters the idle state 5 The IDLE output CPU signal is activated driven high 6 The device waits for an enabled or nonmaskable hardware interrupt If such an interrupt occurs the IDLESTAT bit is...

Page 256: ...ore entering the idle mode IDLESTAT is set after exiting the idle mode IDLESTAT is cleared Repeat This instruction is not repeatable If this instruction follows the RPT instruc tion it resets the repe...

Page 257: ...and accumulate First add the unsigned previous product stored in the P register ignoring the product shift mode PM to the ACC register Then multiply the signed 32 bit content of the location pointed t...

Page 258: ...else Z is cleared g Modes N After the addition the N flag is set if bit 31 of the ACC is 1 else N is cleared C If the addition generates a carry C is set otherwise C is cleared V If an overflow occurs...

Page 259: ...et product shift to 5 ZAPA Zero ACC P OVCU RPT N 1 Repeat next instruction N times IMACL P XAR2 XAR7 OVCU ACC OVCU ACC P P X i C i 5 i ADDUL ACC P OVCU ACC OVCU ACC P MOVL sum 0 ACC Store low 32 bits...

Page 260: ...signed loc32 if PM 4 shift P 31 4 temp 27 0 P 3 0 0 if PM 1 shift P 31 1 temp 30 0 P 0 0 if PM 0 shift P 31 0 temp 31 0 if PM 1 shift P 31 0 temp 32 1 if PM 2 shift P 31 0 temp 33 2 if PM 3 shift P 31...

Page 261: ...C0 2 MOVL XT X1 XT X1 IMPYAL P XT C1 OVCU ACC OVCU ACC P P low 32 bits of X1 C1 2 MOVL XT X2 XT X2 IMPYAL P XT C2 OVCU ACC OVCU ACC P P low 32 bits of X2 C2 2 ADDUL ACC P OVCU ACC OVCU ACC P MOVL Y64...

Page 262: ...32 addressing mode and store the lower 32 bits of the 64 bit result in the ACC register ACC signed XT signed loc32 Flags and Z After the operation the Z flag is set if the ACC value is zero else Z is...

Page 263: ...d loc32 if PM 4 shift P 31 4 temp 27 0 P 3 0 0 if PM 1 shift P 31 1 temp 30 0 P 0 0 if PM 0 shift P 31 0 temp 31 0 if PM 1 shift P 31 0 temp 32 1 if PM 2 shift P 31 0 temp 33 2 if PM 3 shift P 31 0 te...

Page 264: ...loc32 if PM 4 shift P 31 4 temp 27 0 P 3 0 0 if PM 1 shift P 31 1 temp 30 0 P 0 0 if PM 0 shift P 31 0 temp 31 0 if PM 1 shift P 31 0 temp 32 1 if PM 2 shift P 31 0 temp 33 2 if PM 3 shift P 31 0 tem...

Page 265: ...XT X1 XT X1 IMPYSL P XT C1 OVCU ACC OVCU ACC P P low 32 bits of X1 C1 2 MOVL XT X2 XT X2 IMPYSL P XT C2 OVCU ACC OVCU ACC P P low 32 bits of X2 C2 2 SUBUL ACC P OVCU ACC OVCU ACC P MOVL Y64 0 ACC Stor...

Page 266: ...s of the 64 bit result are stored in the P register temp 37 0 lower_38 bits signed XT unsigned loc32 if PM 4 shift P 31 4 temp 27 0 P 3 0 0 if PM 1 shift P 31 1 temp 30 0 P 0 0 if PM 0 shift P 31 0 te...

Page 267: ...VL ACC B0 ACC B0 ADDUL ACC P ACC ACC P MOVL Y0 ACC Store result into Y0 QMPYUL P XT M0 P high 32 bits of uns M0 uns X0 MOVL XT X1 XT X1 MOVL ACC P ACC P IMPYXUL P XT M0 P low 32 bits of uns M0 sign X1...

Page 268: ...lar device for details Flags and Modes N If loc16 AX then after the move AX is tested for a negative condition The negative flag bit is set if bit 15 of AX is 1 otherwise it is cleared Z If loc16 AX t...

Page 269: ...IN loc16 PA 6 112 MOV AL 0 AL 0 UOUT IORegC AL IOspace IORegC AL 10...

Page 270: ...and Modes N After the operation if bit 15 of loc16 1 set N otherwise clear N Z After the operation if loc16 is zero set Z otherwise clear Z C If the addition generates a carry C is set otherwise C is...

Page 271: ...The INTR instruction transfers program control to the interrupt service routine that corresponds to the vector specified by the instruction The INTR instruction is not affected by the INTM bit in stat...

Page 272: ...ear the corresponding IFR bit Flush the pipeline temp PC 1 Fetch specified vector SP SP 1 SP T ST0 SP SP 2 SP AH AL SP SP 2 SP PH PL SP SP 2 SP AR1 AR0 SP SP 2 SP DP ST1 SP SP 2 SP DBGSTAT IER SP SP 2...

Page 273: ...using 32 bit operations The stack pointer is not forced to align to an even address during the register restore operations SP SP 2 PC SP SP SP 2 DBGSTAT IER SP SP SP 2 DP ST1 SP SP SP 2 AR1 AR0 SP SP...

Page 274: ...6 117 DBGM PAGEO VMAP SPA EAL LOW AMODE OBJ MODE XF ARP Repeat This instruction is not repeatable If this instruction follows the RPT instruction it resets the repeat counter RPTC and executes only o...

Page 275: ...stack Return PC saved on stack IER bit corresponding to INTx is disabled ST1 EALLOW bit 0 ST1 LOOP bit 0 ST1 DBGM bit 1 ST1 INTM bit 1 PUSH AR1H AR0H Save remaining registers PUSH XAR2 PUSH XAR3 PUSH...

Page 276: ...t This instruction is not repeatable If this instruction follows the RPT instruction it resets the repeat counter RPTC and executes only once Example Branch to subroutines in SwitchTable selected by S...

Page 277: ...his instruction follows the RPT instruction it resets the repeat counter RPTC and executes only once Example Branch to subroutines in SwitchTable selected by Switch value SwitchTable Switch address ta...

Page 278: ...SP SP 1 PC XAR7 21 0 Note For more efficient function calls when operating with OBJMODE 1 use the LCR and LRETR instructions instead of the LC and LRET instructions Flags and Modes None Repeat This i...

Page 279: ...estination address is loaded onto the PC temp 21 0 PC 2 SP temp 15 0 SP SP 1 SP temp 21 16 SP SP 1 PC 22bit Note For more efficient function calls when operating with OBJMODE 1 use the LCR and LRETR i...

Page 280: ...15 0 SP SP 1 SP RPC 21 16 SP SP 1 RPC PC 2 PC 22bit Note The LCR and LRETR operations enable 4 cycle call and 4 cycle return The standard LC and LRET operations only enable a 4 cycle call and 8 cycle...

Page 281: ...call and 4 cycle return The standard LC and LRET operations only enable a 4 cycle call and 8 cycle return The LCR and LRETR operations can be nested and can freely replace the LC and LRET operations...

Page 282: ...value by using a bitwise AND operation 5 If the result is 0 clear the LOOP bit and increment the PC by 2 If the result is not 0 then return to step 1 The loop created by steps 1 through 5 can be inte...

Page 283: ...owing the LOOPNZ is executed Flags and Modes N If bit 15 of the result of the AND operation is 1 set N otherwise clear N Z If the result of the AND operation is 0 set Z otherwise clear Z LOOP LOOP is...

Page 284: ...ue by using a bitwise AND operation 5 If the result is not 0 clear the LOOP bit and increment the PC by 2 If the result is 0 then return to step 1 The loop created by steps 1 through 5 can be interrup...

Page 285: ...lowing the LOOPZ is executed Flags and N If bit 15 of the result of the AND operation is 1 set N otherwise clear N g Modes Z If the result of the AND operation is 0 set Z otherwise clear Z LOOP LOOP i...

Page 286: ...s AMODE The AMODE bit is set Repeat This instruction is not repeatable If this instruction follows the RPT instruction it resets the repeat counter RPTC and executes only once Example Execute the oper...

Page 287: ...SP PC temp 21 0 Flags and Modes None Note For more efficient function calls when operating with OBJMODE 1 use the LCR and LRETR instructions in place of the LC and LRET instructions Repeat This instru...

Page 288: ...interrupts SP SP 1 temp 31 16 SP SP SP 1 temp 15 0 SP PC temp 21 0 INTM 0 Flags and Modes INTM This instruction enables interrupts by clearing the INTM bit Repeat This instruction is not repeatable I...

Page 289: ...rations enable 4 cycle call and 4 cycle return The standard LC and LRET operations only enable a 4 cycle call and 8 cycle return The LCR and LRETR operations can be nested and can freely replace the L...

Page 290: ...ast bit out Discard other bits Left shift Immediate value Flags and Modes N After the shift if bit 31 of ACC is 1 then the negative flag bit is set otherwise it is cleared Z After the shift if ACC is...

Page 291: ...0 Flags and Modes Z After the shift the Z flag is set if the ACC value is zero else Z is cleared Even if the T register specifies a shift of 0 the content of the ACC register is still tested for the z...

Page 292: ...is stored in the carry bit flag 0 C AX AX Discard other bits Last bit out Left shift Immediate value Flags and Modes N After the shift if bit 15 of AX is 1 then the negative flag bit is set otherwise...

Page 293: ...3 0 Flags and Modes N After the shift if bit 15 of AX is 1 then the negative flag bit is set otherwise it is cleared Even if the T 3 0 register bits specify a shift of 0 the value of AH or AL is still...

Page 294: ...fter the shift if bit 31 of the ACC register is 1 then ACC P is negative and the N bit is set otherwise N is cleared Z After the shift the Z flag is set if the combined 64 bit value of the ACC P is ze...

Page 295: ...ft shift contents of T 5 0 Flags and Modes N After the shift if bit 31 of the ACC register is 1 then ACC P is negative and the N bit is set otherwise N is cleared Z After the shift the Z flag is set i...

Page 296: ...ACC Last bit out or cleared Discard other bits Left shift Contents of T 4 0 Flags and Modes Z After the shift the Z flag is set if the ACC value is zero else Z is cleared Even if the T register specif...

Page 297: ...is stored in the carry flag bit 0 C AX AX Discard other bits Last bit out Right shift Immediate value Flags and Modes N After the shift if bit 15 of AX is 1 then the negative flag bit is set otherwis...

Page 298: ...lags and Modes N After the shift if bit 15 of AX is 1 then the negative flag bit is set otherwise it is cleared Even if the T 3 0 register bits specify a shift of 0 the value of AH or AL is still test...

Page 299: ...d Modes N After the shift if bit 31 of the ACC register is 1 then ACC P is negative and the N bit is set otherwise N is cleared Z After the shift the Z flag is set if the combined 64 bit value of the...

Page 300: ...her bits Last bit out or cleared Flags and Modes N After the shift if bit 31 of the ACC register is 1 then ACC P is negative and the N bit is set otherwise N is cleared Z After the shift the Z flag is...

Page 301: ...and Modes Z After the shift the Z flag is set if the ACC value is zero else Z is cleared Even if the T register specifies a shift of 0 the content of the ACC register is still tested for the zero cond...

Page 302: ...28x forces the upper 6 bits of the program memory address specified by the 0 pma addressing mode to 0x00 when using this form of the MAC instruction This limits the program memory address to the low 6...

Page 303: ...s repeatable If the operation follows a RPT instruction then it will be executed N 1 times The state of the Z N C and OVC flags will reflect the final result The V flag will be set if an intermediate...

Page 304: ...of the location pointed to by the loc16 addressing mode 3 Multiply the signed 16 bit content of the T register by the signed 16 bit content of the program memory location pointed to by the XAR7 regis...

Page 305: ...he shift mode for the output operation from the product register If the product shift value is positive logical left shift operation then the low bits are zero filled If the product shift value is neg...

Page 306: ...tion AX loc16 then the negative flag bit will be set otherwise it will be cleared Z If AX and the contents of the addressed location are equal AX loc16 then the zero flag bit will be set otherwise it...

Page 307: ...Z flags will first be set by using a MAXL instruction to compare the upper 32 bits of a 64 bit value The MAXCUL instruction is then used to conditionally compare the lower 32 bits based on the results...

Page 308: ...MAXCUL P loc32 6 151 Saturate MOVL Var64 2 ACC Store result into Var64 MOVL Var64 P...

Page 309: ...0x8000 0000 0x0000 0001 If the precision were limited to 32 bits the result would cause an overflow to the positive number 0x7FFF FFFF and N would be cleared However because the MAXL instruction assu...

Page 310: ...on AX loc16 then the negative flag bit will be set otherwise it will be cleared Z If AX and the contents of the addressed location are equal AX loc16 then the zero flag bit will be set otherwise it wi...

Page 311: ...will first be set by using a MINL instruction to compare the upper 32 bits of a 64 bit value The MINCUL instruction is then used to conditionally compare the lower 32 bits based on the results of the...

Page 312: ...0x8000 0000 0x0000 0001 If the precision were limited to 32 bits the result would cause an overflow to the positive number 0x7FFF FFFF and N would be cleared However because the MINL instruction assu...

Page 313: ...cation specified by the 0 16bit constant address 0x0000 16bit loc16 Flags and Modes None Repeat This instruction is repeatable If the operation follows a RPT instruction then it will be executed N 1 t...

Page 314: ...M 1 sign extension mode enabled ACC S 16bit shift value else sign extension mode disabled ACC 0 16bit shift value Flags and N After the load the N flag is set if bit 31 of the ACC is 1 else N is clear...

Page 315: ...shifted value are zero filled if SXM 1 sign extension mode enabled ACC S loc16 T 3 0 else sign extension mode disabled ACC 0 loc16 T 3 0 Flags and N After the load the N flag is set if bit 31 of the...

Page 316: ...ero extended SXM 0 The lower bits of the shifted value are zero filled if SXM 1 sign extension mode enabled ACC S loc16 shift value else sign extension mode disabled ACC 0 loc16 shift value Flags and...

Page 317: ...7 AR6 or AR7 auxiliary registers loc16 Addressing mode see Chapter 5 Description Load AR6 or AR7 with the contents of the 16 bit location and leave the upper 16 bits of XAR6 and XAR7 unchanged AR6 7 l...

Page 318: ...of the accumulator register unchanged AX loc16 Flags and Modes N The load to AX is tested for a negative condition If bit 15 of AX is 1 then this flag is set otherwise it is cleared Z The load to AX i...

Page 319: ...data page register with a 10 bit constant leaving the upper 6 bits unchanged DP 9 0 10bit DP 15 10 unchanged Flags and Modes None Repeat This instruction is not repeatable If this instruction follows...

Page 320: ...ected interrupts by loading the content of the location pointed to by the loc16 addressing mode into the IER register IER loc16 Flags and Modes None Repeat This instruction is not repeatable If this i...

Page 321: ...ve efficiency To override this use the MOVW AX 16bit alias instruction Flags and Modes N If loc16 AX then the load to AX is tested for a negative condition The negative flag bit is set if bit 15 of AX...

Page 322: ...The negative flag bit is set if bit 15 of AX is 1 otherwise it is cleared Z If loc16 AX then the load to AX is tested for a zero condition The bit is set if the result of the operation on the AX regi...

Page 323: ...negative condition The negative flag bit is set if bit 15 of AX is 1 otherwise it is cleared Z If loc16 AX then the load to AX is tested for a zero condition The bit is set if the result of the operat...

Page 324: ...16 AX then after the load AX is checked for a negative condition The N flag is set if bit 15 of the AX is 1 else N is cleared Z If loc16 AX then after the load AX is checked for a zero condition The Z...

Page 325: ...ister generates a negative value otherwise it is cleared Z If loc16 AX then the load to AX is tested for a zero condition The bit is set if the result of the operation on the AX register generates a 0...

Page 326: ...ve flag bit is set if bit 15 of AX is 1 otherwise it is cleared Z If loc16 AX then the load to AX is tested for a zero condition The bit is set if the result of the operation on the AX register genera...

Page 327: ...O BIO Input Equal To Zero BIO 0 1111 UNC Unconditional Description If the specified condition being tested is true then the location pointed to by the loc16 addressing mode will be loaded with the con...

Page 328: ...ntents of VarA and VarB if VarB is higher then VarA MOV AL VarA AL VarA XAR2 points to VarB MOV AH VarB AH VarB XAR2 points to VarA CMP AH AL Compare AH and AL MOV VarA AH HI Store AH in VarA if highe...

Page 329: ...16 addressing mode loc16 IER Flags and N If loc16 AX and bit 15 of AX is 1 then N is set otherwise N is cleared g Modes Z If loc16 AX and the value of AX is zero then Z is set otherwise Z is cleared R...

Page 330: ...its of the addressed location loc16 15 10 OVC loc16 9 0 0 Flags and N If loc16 AX and bit 15 of AX is 1 then set N otherwise clear N g Modes Z If loc16 AX and AX is zero then set Z otherwise clear Z R...

Page 331: ...then the N bit is set otherwise N is cleared Z If loc16 AX and the value of AX after the load is zero then the Z bit is set otherwise Z is cleared PM The value in the PM bits sets the shift mode for...

Page 332: ...set otherwise N is cleared Z If loc16 AX and the value of AX after the load is zero then the Z bit is set otherwise Z is cleared Repeat This instruction is not repeatable If this instruction follows t...

Page 333: ...y the loc16 addressing mode OVC loc16 15 10 Flags and Modes OVC The 6 bit overflow counter is modified Repeat This instruction is not repeatable If this instruction follows the RPT instruction it rese...

Page 334: ...16 bits of the P register PH with the 16 bit location pointed to by the loc16 addressing mode leave the lower 16 bits PL unchanged PH loc16 PL unchanged Flags and Modes None Repeat This instruction i...

Page 335: ...16 bits of the P register PL with the 16 bit location pointed to by the loc16 addressing mode leave the lower 16 bits PH unchanged PL loc16 PH unchanged Flags and Modes None Repeat This instruction i...

Page 336: ...s are loaded with the 3 least significant bits of AX Repeat This instruction is not repeatable If this instruction follows the RPT instruction it resets the repeat counter RPTC and executes only once...

Page 337: ...addressing mode T loc16 Flags and Modes None Repeat This instruction is not repeatable If this instruction follows the RPT instruction it resets the repeat counter RPTC and executes only once Example...

Page 338: ...lower half of the multiplicand register TL with zero leaving the upper half T unchanged TL 0x0000 T unchanged Flags and Modes None Repeat This instruction is not repeatable If this instruction follow...

Page 339: ...Rn with the contents of the PC XARn 0 PC Flags and Modes None Repeat This instruction is not repeatable If this instruction follows the RPT instruction it resets the repeat counter RPTC and executes o...

Page 340: ...rwise C is cleared V If an overflow occurs V is set otherwise V is not affected OVC If overflow mode is disabled and if the operation generates a positive overflow the counter is incremented If overfl...

Page 341: ...C2 2 X2 X1 X1 X0 SPM 2 Set product shift to 2 MOV T X2 T X2 MPY P T C2 P T C2 MOVP T X1 T X1 ACC X2 C2 2 MPY P T C1 P T C1 MOV X2 T X2 X1 MOVA T X0 T X0 ACC X1 C1 2 X2 C2 2 MPY P T C0 P T C0 MOV X1 T...

Page 342: ...31 of the ACC register is 1 then the N bit is set otherwise N is cleared Z After the operation if the value of ACC is zero then the Z bit is set otherwise Z is cleared C If the addition generates a c...

Page 343: ...xecutes only once Example Calculate using 16 bit multiply Y X0 C0 2 X1 C1 2 X2 C2 2 X2 X1 X1 X0 SPM 2 Set product shift to 2 MOVP T X2 T X2 MPYS P T C2 P T C2 ACC 0 MOVAD T X1 T X1 ACC X2 C2 2 X2 X1 M...

Page 344: ...C 0 8bit Flags and N After the load the N flag is set if bit 31 of the ACC is 1 else N is cleared g Modes Z After the load the Z flag is set if the ACC value is zero else Z is cleared Repeat This inst...

Page 345: ...Operands XARn XAR6 OR XAR7 32 bit auxiliary registers 8bit 8 bit immediate constant value Description Load AR6 or AR7 with an 8 bit unsigned constant and upper 16 bits of XAR6 and XAR7 are unchanged...

Page 346: ...zero extended leaving the other half of the accumulator register unchanged AX 0 8bit Flags and Modes N Flag always set to zero Z The load to AX is tested for a zero condition The bit is set if the op...

Page 347: ...operand determines which of its 8 bits are used to load AX LSB if loc16 XARn offset if offset is an even number AX LSB loc16 LSB if offset is an odd value AX LSB loc16 MSB else AX LSB loc16 LSB AX MSB...

Page 348: ...e byte order in the 32 bit Var32 location Before operation Var32 B3 B2 B1 B0 After operation Var32 B0 B1 B2 B3 MOVL XAR2 Var32 Load XAR2 with address of Var32 MOVB AL LSB XAR2 3 ACC B0 Var32 B3 ACC B1...

Page 349: ...d determines which of its 8 bits are used to load AX MSB if loc16 XARn offset if offset is an even value AX MSB loc16 LSB if offset is an odd value AX MSB loc16 MSB else AX MSB loc16 LSB AX LSB unchan...

Page 350: ...e byte order in the 32 bit Var32 location Before operation Var32 B3 B2 B1 B0 After operation Var32 B0 B1 B2 B3 MOVL XAR2 Var32 Load XAR2 with address of Var32 MOVB AL LSB XAR2 3 ACC B0 Var32 B3 ACC B1...

Page 351: ...ow V 1 1100 NTC Test Bit Not Set TC 0 1101 TC Test Bit Set TC 1 1110 NBIO BIO Input Equal To Zero BIO 0 1111 UNC Unconditional Description If the specified condition being tested is true then the 8 bi...

Page 352: ...truction is not repeatable If this instruction follows the RPT instruction it resets the repeat counter RPTC and executes only once Example Calculate if VarA 20 VarA 0 CMP VarA 20 Set flags on VarA 20...

Page 353: ...6 XARn offset if offset is an even value loc16 LSB AX LSB loc16 MSB unchanged if offset is an odd value loc16 LSB unchanged loc16 MSB AX LSB else loc16 LSB AX LSB loc16 MSB unchanged Note offset 3 bit...

Page 354: ...ce Example Store the 32 bit contents of the ACC into the 32 bit contents of Var32 location in reverse byte order Before operation ACC B3 B2 B1 B0 After operation Var32 B0 B1 B2 B3 MOVL XAR2 Var32 Load...

Page 355: ...XARn offset if offset is an even number loc16 LSB AX MSB loc16 MSB unchanged if offset is an odd number loc16 LSB unchanged loc16 MSB AX MSB else loc16 LSB AX MSB loc16 MSB unchanged Note offset 3 bit...

Page 356: ...ce Example Store the 32 bit contents of the ACC into the 32 bit contents of Var32 location in reverse byte order Before operation ACC B3 B2 B1 B0 After operation Var32 B0 B1 B2 B3 MOVL XAR2 Var32 Load...

Page 357: ...it 1011 0110 CCCC CCCC 1 1 Operands XARn XAR0 to XAR7 32 bit auxiliary registers 8bit 8 bit immediate constant value Description Load XARn with the 8 bit unsigned immediate value XARn 0 8bit Flags and...

Page 358: ...and then load the next highest 32 bit location pointed to by loc32 with the content of XT XT loc32 loc32 2 XT Flags and Modes None Repeat This instruction is not repeatable If this instruction follows...

Page 359: ...then after the load AX is checked for a negative condition The N flag is set if bit 15 of the AX is 1 else N is cleared Z If loc16 AX then after the load AX is checked for a zero condition The Z flag...

Page 360: ...then the N bit is set otherwise N is cleared Z If loc16 AX and the value of AX after the load is zero then the Z bit is set otherwise Z is cleared PM The value in the PM bits sets the shift mode for...

Page 361: ...ing mode ACC loc32 Flags and Modes N After the load the N flag is set if bit 31 of the ACC is 1 else N is cleared Z After the load the Z flag is set if the ACC is zero else Z is cleared Repeat This in...

Page 362: ...1 else N is cleared Z After the load the Z flag is set if the ACC is zero else Z is cleared PM The value in the PM bits sets the shift mode for the output operation from the product register If the pr...

Page 363: ...C Flags and Modes N If loc32 ACC then after the load the N flag is set if bit 31 of the ACC is 1 else N is cleared Z If loc32 ACC then after the load the Z flag is set if ACC is zero else Z is cleared...

Page 364: ...1 0110 HI Higher C 1 AND Z 0 0111 HIS C Higher Or Same Carry Set C 1 1000 LO NC Lower Carry Clear C 0 1001 LOS Lower Or Same C 0 OR Z 1 1010 NOV No Overflow V 0 1011 OV Overflow V 1 1100 NTC Test Bit...

Page 365: ...ared V If the V flag is tested by the condition then V is cleared Repeat This instruction is not repeatable If this instruction follows the RPT instruction it resets the repeat counter RPTC and execut...

Page 366: ...n the Z bit is set otherwise Z is cleared Repeat This instruction is not repeatable If this instruction follows the RPT instruction it resets the repeat counter RPTC and executes only once Example Add...

Page 367: ...ster is the sign bit 0 for positive 1 for negative The negative flag bit is set if the operation on the ACC register generates a negative value otherwise it is cleared Z If loc32 ACC then the load to...

Page 368: ...he value of ACC after the load is zero then the Z bit is set otherwise Z is cleared Repeat This instruction is not repeatable If this instruction follows the RPT instruction it resets the repeat count...

Page 369: ...Repeat This instruction is not repeatable If this instruction follows the RPT instruction it resets the repeat counter RPTC and executes only once Example Calculate the 32 bit value VarC abs VarA abs...

Page 370: ...tion follows the RPT instruction it resets the repeat counter RPTC and executes only once Example Add 64 bit VarA VarB and VarC and store result in VarD MOVL P VarA 0 Load P with low 32 bits of VarA M...

Page 371: ...liary registers loc32 Addressing mode see Chapter 5 Description Load XARn with the contents of the 32 bit addressed location XARn loc32 Flags and Modes None Repeat This instruction is not repeatable I...

Page 372: ...C CCCC CCCC CCCC 1 1 MOVL XAR5 22bit 1000 1111 01CC CCCC CCCC CCCC CCCC CCCC 1 1 MOVL XAR6 22bit 0111 0110 10CC CCCC CCCC CCCC CCCC CCCC X 1 MOVL XAR7 22bit 0111 0110 11CC CCCC CCCC CCCC CCCC CCCC X 1...

Page 373: ...s None Repeat This instruction is not repeatable If this instruction follows the RPT instruction it resets the repeat counter RPTC and executes only once Example Calculate using 32 bit multiply retain...

Page 374: ...value of ACC is zero then the Z bit is set otherwise Z is cleared PM The value in the PM bits sets the shift mode for the output operation from the product register If the product shift value is posi...

Page 375: ...otherwise C is set V If an overflow occurs V is set otherwise V is not affected OVC If overflow mode is disabled and if the operation generates a positive overflow then the counter is incremented If o...

Page 376: ...2 X2 X1 X1 X0 SPM 2 Set product shift to 2 MOVP T X2 T X2 MPYS P T C2 P T C2 ACC 0 MOVS T X1 T X1 ACC X2 C2 2 MPY P T C1 P T C1 MOV X2 T X2 X1 MOVA T X0 T X0 ACC X1 C1 2 X2 C2 2 MPY P T C0 P T C0 MOV...

Page 377: ...he accumulator AH with 0s AL loc16 AH 0x0000 Flags and Modes N Clear flag Z After the load the Z flag is set if the ACC value is zero else Z is cleared Repeat This instruction is not repeatable If thi...

Page 378: ...er 10 bits of the addressed location loc16 15 6 0 loc16 5 0 OVC Flags and Modes N If loc16 AX and bit 15 of AX is 1 then set N otherwise clear N Z If loc16 AX and AX is zero then set Z otherwise clear...

Page 379: ...nted to by the loc16 addressing mode OVC loc16 5 0 Flags and Modes OVC The 6 bit overflow counter is modified Repeat This instruction is not repeatable If this instruction follows the RPT instruction...

Page 380: ...alue Description Load the data page register with a 16 bit constant DP 15 0 16bit Flags and Modes None Repeat This instruction is not repeatable If this instruction follows the RPT instruction it rese...

Page 381: ...d register TL with the 16 bit contents of the location pointed to by the loc16 addressing mode and then sign extend that value into the upper upper 16 bits of XT TL loc16 T sign extension of TL Flags...

Page 382: ...c16 Addressing modes See chapter 5 Description Load ARn with the contents of the 16 bit location and clear ARnH ARn loc16 ARnH 0 Flags and Modes None Repeat This instruction is not repeatable If this...

Page 383: ...d the data page register with a 10 bit constant and clear the upper 6 bits DP 9 0 10bit DP 15 10 0 Flags and Modes None Repeat This instruction is not repeatable If this instruction follows the RPT in...

Page 384: ...then multiply the signed 16 bit content of the T register by the specified signed 16 bit constant value T loc16 ACC signed T signed 16bit Flags and Modes Z After the operation the Z flag is set if th...

Page 385: ...to by the loc16 addressing mode and store the result in the ACC register ACC signed T signed loc16 Flags and Modes Z After the operation the Z flag is set if the ACC is zero else Z is cleared N After...

Page 386: ...16 bit immediate value and store the 32 bit result in the P register P signed loc16 signed 16bit Flags and Modes None Repeat This instruction is not repeatable If this instruction follows the RPT ins...

Page 387: ...d store the 32 bit result in the P register P signed T signed loc16 Flags and Modes None Repeat This instruction is not repeatable If this instruction follows the RPT instruction it resets the repeat...

Page 388: ...N flag is set if bit 31 of the ACC is 1 else N is cleared C If the addition generates a carry C is set otherwise C is cleared V If an overflow occurs V is set otherwise V is not affected OVC If overf...

Page 389: ...X0 C0 2 X1 C1 2 X2 C2 2 C0 C1 and C2 are constants SPM 2 Set product shift to 2 MOVB ACC 0 Zero ACC MPY P X2 C2 P X2 C2 MPYA P X1 C1 ACC X2 C2 2 P X1 C1 MPYA P X0 C0 ACC X1 C1 2 X2 C2 2 P X0 C0 ADDL A...

Page 390: ...otherwise C is cleared V If an overflow occurs V is set otherwise V is not affected OVC If overflow mode is disabled and if the operation generates a positive overflow then the counter is incremented...

Page 391: ...2 X1 C1 2 X2 C2 2 SPM 2 Set product shift to 2 MOVP T X2 ACC P T X2 MPYS P T C2 ACC ACC P 0 P T C2 MOV T X1 T X1 MPYA P T C1 ACC X2 C2 2 P T C1 MOV T X0 T X0 MPYA P T C0 ACC X1 C1 2 X2 C2 2 P T C0 ADD...

Page 392: ...nt value zero extended and store the result in the ACC register ACC signed T 0 8bit Flags and Modes Z After the operation the Z flag is set if the ACC is zero else Z is cleared N After the operation t...

Page 393: ...escription Multiply the signed 16 bit content of the T register by the unsigned 8 bit immediate constant value zero extended and store the 32 bit result in the P register P signed T 0 8bit Flags and M...

Page 394: ...cleared V If an overflow occurs V is set otherwise V is not affected OVC If overflow mode is disabled and if the operation generates a positive overflow then the counter is incremented If overflow mo...

Page 395: ...2 X1 C1 2 X2 C2 2 SPM 2 Set product shift to 2 MOVP T X2 ACC P T X2 MPYS P T C2 ACC ACC P 0 P T C2 MOV T X1 T X1 MPYA P T C1 ACC X2 C2 2 P T C1 MOV T X0 T X0 MPYA P T C0 ACC X1 C1 2 X2 C2 2 P T C0 ADD...

Page 396: ...content of the T register by the signed 16 bit contents of the location pointed to by the loc16 addressing mode and store the 32 bit result in the P register P unsigned T unsigned loc16 Flags and Mode...

Page 397: ...to by the loc16 addressing mode and store the 32 bit results in the ACC register ACC unsigned T unsigned loc16 Flags and Modes Z After the operation the Z flag is set if the ACC is zero else Z is clea...

Page 398: ...o by the loc16 addressing mode and store the result in the ACC register ACC signed T unsigned loc16 Flags and Modes Z After the operation the Z flag is set if the ACC is zero else Z is cleared N After...

Page 399: ...e P register P signed T unsigned loc16 Flags and Modes None Repeat This instruction is not repeatable If this instruction follows the RPT instruction it resets the repeat counter RPTC and executes onl...

Page 400: ...instruction If the SPA bit is 0 then the NASP instruction performs no operation if SPA 1 SP SP 1 SPA 0 Flags and Modes PSA If SPA 1 then SPA is cleared Repeat This instruction is not repeatable If thi...

Page 401: ...x8000 0000 at the start of the operation this is considered an overflow value and V is set Otherwise V is not affected OVM If ACC 0x8000 0000 at the start of the operation this is considered an overfl...

Page 402: ...ed Z After the operation if AX is 0 then the Z bit is set otherwise it is cleared C If AX is 0 C is set otherwise it is cleared V If AX is 0x8000 at the start of the operation then this is considered...

Page 403: ...negative and the N bit is set otherwise N is cleared Z After the operation the Z flag is set if the combined 64 bit value of the ACC P is zero otherwise Z is cleared C If ACC P 0 then the C bit is set...

Page 404: ...VL ACC Var64 2 Load ACC with high 32 bits of Var64 MOVL P Var64 0 Load P with low 32 bits of Var64 SETC OVM Enable overflow mode saturate NEG64 ACC P Negate ACC P with saturation MOVL Var64 2 ACC Stor...

Page 405: ...is set if the ACC is zero else Z is cleared C If TC 1 AND ACC 0 set C if TC 1 AND ACC 0 clear C otherwise C is not modified V If TC 1 AND ACC 0x8000 0000 at the start of the operation this is consider...

Page 406: ...ake abs value TC sign TC MOV T AH Temp save Den16 in T register MOV ACC Num16 16 AH Num16 AL 0 ABSTC ACC Take abs value TC sign TC MOVU ACC AH AH 0 AL Num16 RPT 15 Repeat operation 16 times SUBCU T Co...

Page 407: ...This instruction is repeatable If this instruction follows the RPT instruction it will execute N 1 times Example Copy the contents of Array1 to Array2 int32 Array1 N int32 Array2 N for i 0 i N i Array...

Page 408: ...xtra sign bit and the selected pointer is modified If the bits are different the ACC is not shifted and the selected pointer is not modified The selected pointer does not access any memory location Fl...

Page 409: ...l contain shift value at the end of the operation MOVL ACC VarA ACC VarA MOVB XAR2 0 Initialize XAR2 to zero NOP ARP2 Set ARP pointer to point to XAR2 SBF Skip EQ Skip if ACC value is zero RPT 31 Repe...

Page 410: ...ally shifted left by 1 to eliminate the extra sign bit and the selected pointer is modified If the bits are different the ACC is not shifted and the selected pointer is not modified The selected point...

Page 411: ...ts of VarA XAR2 will contain shift value at the end of the operation MOVL ACC VarA ACC VarA MOVB XAR2 0 Initialize XAR2 to zero SBF Skip EQ Skip if ACC value is zero RPT 31 Repeat next operation 32 ti...

Page 412: ...s and Modes N After the operation the N flag is set if bit 31 of the ACC is 1 else N is cleared Z After the operation the Z flag is set if the ACC is zero else Z is cleared Repeat This instruction is...

Page 413: ...s and Modes N After the operation if bit 15 of AX is 1 then the negative flag bit is set otherwise it is cleared Z After the operation if AX is 0 then the Z bit is set otherwise it is cleared Repeat T...

Page 414: ...d to ACC is tested for a negative condition If bit 31 of ACC is 1 then the negative flag bit is set otherwise it is cleared Z The load to ACC is tested for a zero condition The zero flag bit is set if...

Page 415: ...are zero filled before the OR operation The result is stored in the ACC register ACC ACC OR 0 16bit shift value Flags and Modes N The load to ACC is tested for a negative condition If bit 31 of ACC i...

Page 416: ...16 Flags and Modes N The load to AX is tested for a negative condition If bit 15 of AX is 1 then the negative flag bit is set otherwise it is cleared Z The load to AX is tested for a zero condition Th...

Page 417: ...c interrupts by performing a bitwise OR operation with the IER register and the 16 bit immediate value The result is stored in the IER register IER IER OR 16bit Flags and Modes None Repeat This instru...

Page 418: ...ster IFR IFR OR 16bit Note Interrupt hardware has priority over CPU instruction operation in cases where the interrupt flag is being simultaneously modified by the hardware and the instruction This in...

Page 419: ...by loc16 loc16 loc16 OR 16bit Smart Encoding If loc16 AH or AL and 16bit is an 8 bit number then the assembler will encode this instruction as ORB AX 8bit to improve efficiency To override this encodi...

Page 420: ...oc16 OR AX This instruction performs a read modify write operation Flags and Modes N The load to loc16 is tested for a negative condition If bit 15 of loc16 is 1 then the negative flag bit is set othe...

Page 421: ...8bit Flags and Modes N The load to AX is tested for a negative condition If bit 15 of AX is 1 then the negative flag bit is set otherwise it is cleared Z The load to AX is tested for a zero condition...

Page 422: ...IN will occur before the UOUT To be certain of the sequence of operation use the OUT instruction which is pipeline protected Note The UOUT operation is not pipeline protected Therefore if an IN instr...

Page 423: ...OUT PA loc16 6 266 IN AL IORegC AL IOspace IORegC CMP AL 0x2000 Set flags on AL 0x2000 SB 10 NEQ Branch if not equal MOV AL 0 AL 0 UOUT IORegC AL IOspace IORegC AL 10...

Page 424: ...ndition Bit 31 of the ACC register is the sign bit 0 for positive 1 for negative The negative flag bit is set if the operation on the ACC register generates a negative value otherwise it is cleared Z...

Page 425: ...scription AR1 AR0 or AR3 AR2 or AR5 AR4 Predecrement SP by 2 Load the contents of two 16 bit auxiliary registers ARn and ARm with the value pointed to by SP and SP 1 POP AR1 AR0 SP 2 AR0 SP AR1 SP 1 A...

Page 426: ...of the auxiliary registers AR0 and AR1 are left unchanged SP 2 AR0H SP AR1H SP 1 AR1 AR0 unchanged Flags and Modes None Repeat This instruction is not repeatable If this instruction follows the RPT i...

Page 427: ...5 Operands DBGIER Debug interrupt enable register Description Predecrement SP by 1 Load the contents of DBGIER with the value pointed to by SP SP 1 DBGIER SP Flags and Modes None Repeat This instructi...

Page 428: ...00 0011 X 1 Operands DP Data page register Description Predecrement SP by 1 Load the contents of DP with the value pointed to by SP SP 1 DP SP Flags and Modes None Repeat This instruction is not repea...

Page 429: ...data page register and status register 1 Description Predecrement SP by 2 Load ST1 with the value pointed to by SP and load DP with the value pointed to by SP 1 SP 2 ST1 SP DP SP 1 Flags and Modes Non...

Page 430: ...X 5 Operands IFR Interrupt flag register Description Predecrement SP by 1 Load the contents of IFR with the value pointed to by SP SP 1 IFR SP Flags and Modes None Repeat This instruction is not repe...

Page 431: ...ad to AX is tested for a zero condition The bit is set if the result of the operation on the AX register generates a 0 value otherwise it is cleared Repeat This instruction is not repeatable If this i...

Page 432: ...01 0001 X 1 Operands P Product register Description Predecrement SP by 2 Load P with the 32 bit value pointed to by SP SP 2 P SP Flags and Modes None Repeat This instruction is not repeatable If this...

Page 433: ...3 Operands RPC Return program counter register Description Predecrement SP by 2 Load the contents of RPC with the value pointed to by SP SP 2 RPC SP Flags and Modes None Repeat This instruction is no...

Page 434: ...ecrement SP by 1 Load the contents of ST0 with the value pointed to by SP SP 1 ST0 SP Flags and Modes c The bit value of each flag and mode listed is replaced by the value popped off of the stack N V...

Page 435: ...Load the contents of ST0 with the value pointed to by SP SP 1 ST1 SP Flags and Modes DBGM The bit values for each flag and mode listed is replaced by the value popped off of the stack INTM VMAP SPA PA...

Page 436: ...status register 0 Description Predecrement SP by 2 Load ST0 with the value pointed to by SP and load T with the value pointed to by SP 1 The low 16 bits of the XT Register TL are left unchanged SP 2 T...

Page 437: ...it auxiliary registers Description Predecrement SP by 2 Load XARn with the 32 bit value pointed to by SP SP 2 XARn SP Flags and Modes None Repeat This instruction is not repeatable If this instruction...

Page 438: ...1110 X 1 Operands XT Multiplicand register Description Predecrement SP by 2 Load XT with the 32 bit value pointed to by SP SP 2 XT SP Flags and Modes None Repeat This instruction is not repeatable If...

Page 439: ...space address range With some addressing mode combinations you can get conflicting references In such cases the C28x will give the loc16 loc32 field priority on changes to XAR7 For example PREAD XAR7...

Page 440: ...PREAD loc16 XAR7 6 283 MOVL XAR2 Array2 XAR2 pointer to Array2 RPT N 1 Repeat next instruction N times PREAD XAR2 XAR7 Array2 i Array1 i i...

Page 441: ...ACC onto the stack pointed to by SP Post increment SP by 2 SP ACC SP 2 Flags and Modes None Repeat This instruction is not repeatable If this instruction follows the RPT instruction it resets the repe...

Page 442: ...R0 or AR3 AR2 or AR5 AR4 auxiliary registers Description Push the contents of two 16 bit auxiliary registers ARn and ARm onto the stack pointed to by SP Post increment SP by 2 PUSH AR1 AR0 SP AR0 SP 1...

Page 443: ...ent SP by 2 SP AR0H SP 1 AR1H SP 2 Flags and Modes None Repeat This instruction is not repeatable If this instruction follows the RPT instruction it resets the repeat counter RPTC and executes only on...

Page 444: ...1 Operands DBGIER Debug interrupt enable register Description Push the 16 bit contents of DBGIER onto the stack pointed to by SP Post increment SP by 1 SP DBGIER SP 1 Flags and Modes None Repeat This...

Page 445: ...1 X 1 Operands DP Data page register Description Push the 16 bit contents of DP onto the stack pointed to by SP Post increment SP by 1 SP DP SP 1 Flags and Modes None Repeat This instruction is not re...

Page 446: ...register and status register 1 Description Push the 16 bit contents of ST1 followed by the 16 bit contents of DP onto the stack pointed to by SP Post increment SP by 2 SP ST1 SP 1 DP SP 2 Flags and M...

Page 447: ...Operands IFR Interrupt flag register Description Push the 16 bit contents of IFR onto the stack pointed to by SP Post increment SP by 1 SP IFR SP 1 Flags and Modes None Repeat This instruction is not...

Page 448: ...struction is not repeatable If this instruction follows the RPT instruction it resets the repeat counter RPTC and executes only once Example PUSH T Push the contents of XT 31 15 into the location poin...

Page 449: ...increment SP by 2 SP P SP 2 Flags and Modes None Repeat This instruction is not repeatable If this instruction follows the RPT instruction it resets the repeat counter RPTC and executes only once Exa...

Page 450: ...s RPC Return program counter register Description Push the contents of the RPC register onto the stack pointed to by SP Post increment SP by 2 SP RPC SP 2 Flags and Modes None Repeat This instruction...

Page 451: ...1 Operands ST0 Status register 0 Description Push the 16 bit contents of ST0 onto the stack pointed to by SP Post increment SP by 1 SP ST0 SP 1 Flags and Modes None Repeat This instruction is not rep...

Page 452: ...1 Operands ST1 Status register 1 Description Push the 16 bit contents of ST1 onto the stack pointed to by SP Post increment SP by 1 SP ST1 SP 1 Flags and Modes None Repeat This instruction is not rep...

Page 453: ...multiplicand register and status register 0 Description Push the 16 bit contents of ST0 followed by the 16 bit contents of T onto the stack pointed to by SP Post increment SP by 2 SP ST0 SP 1 T SP 2 F...

Page 454: ...register Description Push the 32 bit contents of XARn onto the stack pointed to by SP Post increment SP by 2 SP XARn SP 2 Flags and Modes None Repeat This instruction is not repeatable If this instruc...

Page 455: ...ost increment SP by 2 SP XT SP 2 Flags and Modes None Repeat This instruction is not repeatable If this instruction follows the RPT instruction it resets the repeat counter RPTC and executes only once...

Page 456: ...program space address range With some addressing mode combinations you can get conflicting references In such cases the C28x will give the loc16 loc32 field priority on changes to XAR7 For example PWR...

Page 457: ...d store the upper 32 bits of the 64 bit result in the P register If specified post increment the XAR7 register by 2 ACC ACC P PM P signed T signed Prog XAR7 or XAR7 32 On the C28x devices memory block...

Page 458: ...peatable If the operation follows a RPT instruction then it will be executed N 1 times The state of the Z N C and OVC flags will reflect the final result in the ACC The V flag will be set if an interm...

Page 459: ...N After the addition the N flag is set if bit 31 of the ACC is 1 else N is cleared C If the addition generates a carry C is set otherwise C is cleared V If an overflow occurs V is set otherwise V is...

Page 460: ...roduct shift mode to 2 ZAPA Zero ACC P OVC MOVL XT X0 XT X0 QMPYL P XT C0 P high 32 bits of X0 C0 MOVL XT X1 XT X0 QMPYAL P XT C1 ACC ACC P 2 P high 32 bits of X1 C1 MOVL XT X2 XT X0 QMPYAL P XT C2 AC...

Page 461: ...d store the upper 32 bits of the 64 bit result a Q30 number in the P register P signed XT signed loc32 32 Flags and Modes None Repeat This instruction is not repeatable If this instruction follows the...

Page 462: ...upper 32 bits of the 64 bit result a Q30 number in the ACC register ACC signed XT signed loc32 32 Flags and Modes Z After the operation the Z flag is set if the ACC value is zero else Z is cleared N...

Page 463: ...ion the N flag is set if bit 31 of the ACC is 1 else N is cleared C If the subtraction generates a borrow C is cleared otherwise C is set V If an overflow occurs V is set otherwise V is not affected O...

Page 464: ...roduct shift mode to 2 ZAPA Zero ACC P OVC MOVL XT X0 XT X0 QMPYL P XT C0 P high 32 bits of X0 C0 MOVL XT X1 XT X0 QMPYSL P XT C1 ACC ACC P 2 P high 32 bits of X1 C1 MOVL XT X2 XT X0 QMPYSL P XT C2 AC...

Page 465: ...mode and store the upper 32 bits of the 64 bit result in the P register P unsigned XT unsigned loc32 32 Flags and Modes None Repeat This instruction is not repeatable If this instruction follows the R...

Page 466: ...ollows the RPT instruction it resets the repeat counter RPTC and executes only once Example Calculate signed result Y64 M64 X64 64 B64 Y64 Y1 Y0 M64 M1 M0 X64 X1 X0 B64 B1 B0 MOVL XT X1 XT X1 QMPYXUL...

Page 467: ...31 of the ACC is 1 else N is cleared Z After the operation the Z flag is set if the ACC is zero else Z is cleared C The value in bit 31 of the ACC register is transferred to C The value in C before t...

Page 468: ...t 31 of the ACC is 1 else N is cleared Z After the operation the Z flag is set if the ACC is zero else Z is cleared C The value in bit 0 of the ACC register is transferred to C The value in C before t...

Page 469: ...ote on syntax Parallel bars before the repeated instruction are used as a reminder that the instruction is repeated and is not interruptable When writing inline assembly use the syntax asm RPT 8bt loc...

Page 470: ...cleared V If OVC 0 at the start of the operation V is set otherwise V is cleared OVC If OVC 0 then ACC is saturated to its maximum positive value If OVC 0 then ACC is saturated to its maximum negativ...

Page 471: ...ACC P is negative and the N bit is set otherwise N is cleared Z After the operation the Z flag is set if the combined 64 bit value of the ACC P is zero otherwise Z is cleared C The C bit is cleared V...

Page 472: ...he ACC and then add higher portion of the 64 bit variables MOVB AH 0 Store overlow repeated carry in the ACC and then add higher portion of the 64 bit variables ZAP OVC Clear overflow counter ADDL ACC...

Page 473: ...o Overflow V 0 1011 OV Overflow V 1 1100 NTC Test Bit Not Set TC 0 1101 TC Test Bit Set TC 1 1110 NBIO BIO Input Equal To Zero BIO 0 1111 UNC Unconditional Description Short conditional branch If the...

Page 474: ...d otherwise C is set V If an overflow occurs V is set otherwise V is not affected OVC If OVM 0 disabled then if the operation generates a positive overflow then the counter is incremented and if the o...

Page 475: ...ast conditional branch If the specified condition is true then branch by adding the signed 8 bit constant value to the current PC value otherwise continue execution without branching If tested conditi...

Page 476: ...iary register XAR0 to XAR7 This pointer determines which auxiliary register is modified by the operation Repeat This instruction is not repeatable If this instruction follows the RPT instruction it re...

Page 477: ...specified status bits The mode operand is a mask value that relates to the status bits in this way Mode bit Status Register Flag Cycles 0 ST0 SXM 1 1 ST0 OVM 1 2 ST0 TC 1 3 ST0 C 1 4 ST1 INTM 2 5 ST1...

Page 478: ...ngs SETC INTM DBGM Set INTM and DBGM bits to 1 CLRC TC C SXM OVM Clear TC C SXM OVM bits to 0 CLRC 0xFF Clear all bits to 0 SETC 0xFF Set all bits to 1 SETC C SXM TC OVM Set TC C SXM OVM bits to 1 CLR...

Page 479: ...to 0x7FF C27x M1 0x400 to 0x7FF M1 0x000 to 0x3FF 1 M0 0x000 to 0x3FF C28x C2XLP M1 0x400 to 0x7FF Note The pipeline is flushed when this instruction is executed Flags and Modes M0M1MAP The M0M1MAP bi...

Page 480: ...pports C2XLP source Flags and Modes OBJMODE Set the OBJMODE bit Repeat This instruction is not repeatable If this instruction follows the RPT instruction it resets the repeat counter RPTC and executes...

Page 481: ...orresponding output signal high Flags and Modes XF The XF status bit is set Repeat This instruction is not repeatable If this instruction follows the RPT instruction it resets the repeat counter RPTC...

Page 482: ...and Modes Z After the shift the Z flag is set if the ACC value is zero else Z is cleared N After the shift the N flag is set if bit 31 of the ACC is 1 else N is cleared C The last bit shifted out is...

Page 483: ...0 the content of the ACC register is still tested for the zero condition and Z is affected N After the shift the N flag is set if bit 31 of the ACC is 1 else N is cleared Even if the T register speci...

Page 484: ...positive numbers indicate a logical left shift The following table shows the relationship between the shift operand and the 3 bit value that gets loaded into the product shift mode PM bits in ST0 The...

Page 485: ...ample Calculate Y32 M16 X16 4 B32 CLRC AMODE Make sure AMODE 0 SPM 4 Set product shift mode to 4 MOV T X16 T X16 MPY P XT M16 P X16 M16 MOVL ACC B32 ACC B32 ADDL ACC P PM ACC ACC P 4 MOVL Y32 ACC Stor...

Page 486: ...erflow occurs V is set otherwise V is not affected OVC If overflow mode is disabled and if the operation generates a positive overflow then the counter is incremented If overflow mode is disabled and...

Page 487: ...ata information sum 0 for i 0 i N i sum sum X i X i 5 MOVL XAR2 X XAR2 pointer to X SPM 5 Set product shift to 5 ZAPA Zero ACC P OVC RPT N 1 Repeat next instruction N times SQRA XAR2 ACC ACC P 5 P XAR...

Page 488: ...If an overflow occurs V is set otherwise V is not affected OVC If overflow mode is disabled and if the operation generates a positive overflow then the counter is incremented If overflow mode is disab...

Page 489: ...N Data information sum 0 for i 0 i N i sum sum X i X i 5 MOVL XAR2 X XAR2 pointer to X SPM 5 Set product shift to 5 ZAPA Zero ACC P OVC RPT N 1 Repeat next instruction N times SQRS XAR2 ACC ACC P 5 P...

Page 490: ...sion mode disabled ACC ACC 0 loc16 shift value Flags and Modes Z After the subtraction the Z flag is set if ACC is zero else Z is cleared N After the subtraction the N flag is set if bit 31 of the ACC...

Page 491: ...e set if an intermediate overflow occurs The OVC flag will count intermediate overflows if overflow mode is disabled If the operation is not repeatable the instruction will execute only once Example C...

Page 492: ...if the ACC value is zero else Z is cleared N After the subtraction the N flag is set if bit 31 of the ACC is 1 else N is cleared C If the subtraction generates a borrow C is cleared otherwise C is set...

Page 493: ...lue ACC VarA SB VarB SB SETC SXM Turn sign extension mode on MOV T SA Load T with shift value in SA MOV ACC VarA T Load in ACC shifted contents of VarA MOV T SB Load T with shift value in SB SUB ACC V...

Page 494: ...et if ACC is zero else Z is cleared g Modes N After the subtraction the N flag is set if bit 31 of the ACC is 1 N is cleared C If the subtraction generates a borrow C is cleared otherwise C is set V I...

Page 495: ...X is tested for a zero condition The zero flag bit is set if the operation generates AX 0 otherwise it is cleared C If the subtraction generates a borrow C is cleared otherwise C is set V If an overfl...

Page 496: ...loc16 is tested for a zero condition The zero flag bit is set if the operation generates loc16 0 otherwise it is cleared C If the subtraction generates a borrow C is cleared otherwise C is set V If a...

Page 497: ...V is set otherwise V is not affected OVC If OVM 0 disabled then if the operation generates a positive overflow then the counter is incremented and if the operation generates a negative overflow then...

Page 498: ...tant to SP and store the result in SP SP SP 0 7bit Flags and Modes None Repeat This instruction is not repeatable If this instruction follows the RPT instruction it resets the repeat counter RPTC and...

Page 499: ...nstant value Description Subtract the 7 bit unsigned constant from XARn and store the result in XARn XARn XARn 0 7bit Flags and Modes None Repeat This instruction is not repeatable If this instruction...

Page 500: ...et V If an overflow occurs V is set otherwise V is not affected OVC If OVM 0 disabled then if the operation generates a positive overflow then the counter is incremented and if the operation generates...

Page 501: ...SUBBL ACC loc32 6 344 SUBBL ACC VarB 2 Subtract from ACC the contents of the high 32 bits of VarB with borrow MOVL VarC 2 ACC Store high 32 bit result into VarC...

Page 502: ...on The final Quotient result must be negated if the Numerator and Denominator values were of different sign else the quotient is left unchanged Flags and Modes Z At the end of the operation the Z flag...

Page 503: ...Store high 16 bit in Quot32 MOV AL Num32 0 AL low 16 bits of Num32 RPT 15 Repeat operation 16 times SUBCU ACC Den16 Conditional subtract with Den16 MOV Rem16 AH Store remainder in Rem16 MOV Quot32 0 A...

Page 504: ...rform signed modulus division the Numerator and Denominator values must be converted to unsigned quantities before executing the SUBCUL instruction The final Quotient result must be negated if the Num...

Page 505: ...value TC sign TC MOVL P ACC Load P register with numerator MOVB ACC 0 Zero ACC RPT 31 Repeat operation 32 times SUBCUL ACC XT Conditional subtract with denominator MOVL Rem32 ACC Store remainder in Re...

Page 506: ...ke absolute value TC sign TC MOVL XT ACC Temp save denominator in XT register MOVB ACC 0 Zero ACC RPT 31 Repeat operation 32 times SUBCUL ACC XT Conditional subtract with denominator MOVL XAR4 P Store...

Page 507: ...erflow occurs V is set otherwise V is not affected OVC If OVM 0 disabled then if the operation generates a positive overflow then the counter is incremented and if the operation generates a negative o...

Page 508: ...s incremented if the operation generates a negative overflow the counter is decremented If OVM 1 enabled the counter is not affected by the operation OVM If overflow mode bit is set then the ACC value...

Page 509: ...SUBL ACC P PM 6 352 SUBL ACC P PM ACC S B 11 M X 4 MOVH Y ACC 5 Store Q15 result into Y...

Page 510: ...tion generates a borrow C is cleared otherwise C is set V If an overflow occurs V is set otherwise V is not affected OVC If OVM 0 disabled and the operation generates a positive overflow the counter i...

Page 511: ...tested for a zero condition The zero flag bit is set if the operation generates loc16 0 otherwise it is cleared C If the subtraction generates a borrow C is cleared otherwise C is set V If an overflow...

Page 512: ...C If the subtraction generates a borrow C is cleared otherwise C is set V If an overflow occurs V is set otherwise V is not affected OVC If OVM 0 disabled then if the operation generates a positive o...

Page 513: ...nd the operation generates a positive overflow the counter is incremented and if the operation generates a negative overflow the counter is decremented If OVM 1 enabled the counter is not affected by...

Page 514: ...ed N After the subtraction the N flag is set if bit 31 of the ACC is 1 else N is cleared C If the subtraction generates a borrow C is cleared otherwise C is set V If an overflow occurs V is set otherw...

Page 515: ...et if the P value is zero else Z is cleared N After the subtraction the N flag is set if bit 31 of P is 1 else N is cleared C If the subtraction generates a borrow C is cleared otherwise C is set V If...

Page 516: ...it number For example if bit 0 you will access bit 0 least significant bit of the addressed location if bit 15 you will access bit 15 most significant bit Flags and Modes TC If the bit tested is 1 TC...

Page 517: ...corresponds to bit 0 least significant bit A value of 0 in the T register corresponds to bit 15 most significant bit The upper 12 bits of the T register are ignored Flags and Modes TC If the bit test...

Page 518: ...ess bit 0 least significant bit of the addressed location if bit 15 you will access bit 15 most significant bit TCLR performs a read modify write operation Flags and Modes N If loc16 AX and bit 15 MSB...

Page 519: ...lag bits accordingly Modify flags on ACC 0x00000000 Flags and Modes N If bit 31 of the ACC is 1 N is set else N is cleared Z If ACC is zero Z is set else Z is cleared Repeat This instruction is not re...

Page 520: ...bit INTM in status register ST1 It also not affected by the enable bits in the IER or the debug interrupt enable register DBGIER Once the TRAP instruction reaches the decode phase of the pipeline hard...

Page 521: ...t only forces execution of the interrupt service routine that corresponds to the RESET interrupt vector Flush the pipeline temp PC 1 Fetch specified vector SP SP 1 SP T ST0 SP SP 2 SP AH AL SP SP 2 SP...

Page 522: ...cess bit 0 least significant bit of the addressed location if bit 15 you will access bit 15 most significant bit TSET performs a read modify write operation Flags and Modes N If loc16 AX and bit 15 MS...

Page 523: ...oggled during the operation The I O address appears on the lower 16 address lines XA 15 0 and the upper address lines are zeroed The data appears on the lower 16 data lines XD 15 0 Note The UOUT opera...

Page 524: ...ne IORegA address IORegB set 0x0301 Define IORegB address IORegC set 0x0302 Define IORegC address MOV AL 0 AL 0 UOUT IORegA AL IOspace IORegA AL MOV AL 0x0400 AL 0x0400 UOUT IORegB AL IOspace IORegB A...

Page 525: ...e of program space 0x3F0000 to 0x3FFFFF Flags and Modes None Repeat This instruction is not repeatable If this instruction follows the RPT instruction it resets the repeat counter RPTC and executes on...

Page 526: ...so change the auxiliary register pointer as specified by the ARPn operand PC 0x3F pma ARP n Note This branch instruction can only branch to a location located in the upper 64K range of program space 0...

Page 527: ...Lower Or Same C 0 OR Z 1 1010 NOV No Overflow V 0 1011 OV Overflow V 1 1100 NTC Test Bit Not Set TC 0 1101 TC Test Bit Set TC 1 1110 NBIO BIO Input Equal To Zero BIO 0 1111 UNC Unconditional Descripti...

Page 528: ...tchTable Switch address table word Switch0 Switch0 address word Switch1 Switch1 address MOVL XAR2 SwitchTable XAR2 pointer to SwitchTable MOVZ AR0 Switch AR0 Switch index MOV AL XAR2 AR0 AL SwitchTabl...

Page 529: ...0x3F0000 to 0x3FFFFF ARPn 3 bit auxiliary register pointer ARP0 to ARP7 Description If the lower 16 bits of the auxiliary register pointed to by the current auxiliary register pointer ARP is not equal...

Page 530: ...rray1 N int32 Array2 N for i 0 i N i Array2 i Array1 i This example only works for code located in upper 64K of program space MOVL XAR2 Array1 XAR2 pointer to Array1 MOVL XAR3 Array2 XAR3 pointer to A...

Page 531: ...er program control to a location located in the upper 64K range of program space 0x3F0000 to 0x3FFFFF To return from a call made by XCALL the XRETC instruction must be used Flags and Modes None Repeat...

Page 532: ...0x3F Then the 3 bit ARP pointer will be set to the ARPn field value temp 21 0 PC 1 SP temp 15 0 SP SP 1 PC 0x3F pma ARP n Note This instruction can only transfer program control to a location located...

Page 533: ...OV Overflow V 1 1100 NTC Test Bit Not Set TC 0 1101 TC Test Bit Set TC 1 1110 NBIO BIO Input Equal To Zero BIO 0 1111 UNC Unconditional Description Conditional call If the specified condition is true...

Page 534: ...is instruction follows the RPT instruction it resets the repeat counter RPTC and executes only once Example Call FuncA if VarA does not equal zero This example only works for code located in upper 64K...

Page 535: ...pecified by the pma addressing mode to 0x3F when using this form of the MAC instruction This limits the program memory address to the high 64K of program address space 0x3F0000 to 0x3FFFFF On the C28x...

Page 536: ...ted N 1 times The state of the Z N C and OVC flags will reflect the final result The V flag will be set if an intermediate overflow occurs When repeated the program memory address is incremented by 1...

Page 537: ...bit result in the P register Last store the content in the T register onto the next highest memory address pointed to by loc16 addressing mode ACC ACC P PM T loc16 P signed T signed Prog 0x3F pma loc...

Page 538: ...hen it will be executed N 1 times The state of the Z N C and OVC flags will reflect the final result The V flag will be set if an intermediate overflow occurs When repeated the program memory address...

Page 539: ...he load to ACC is tested for a negative condition If bit 31 of ACC is 1 then the negative flag bit is set otherwise it is cleared Z The load to ACC is tested for a zero condition The zero flag bit is...

Page 540: ...bits are zero filled before the XOR operation The result is stored in the ACC register ACC ACC XOR 0 16bit shift value Flags and Modes N The load to ACC is tested for a negative condition If bit 31 o...

Page 541: ...AX register AX AX XOR loc16 Flags and Modes N The load to AX is tested for a negative condition If bit 15 of AX is 1 then the negative flag bit is set otherwise it is cleared Z The load to AX is test...

Page 542: ...oc16 loc16 loc16 XOR AX This instruction performs a read modify write operation Flags and Modes N The load to loc16 is tested for a negative condition If bit 15 of loc16 is 1 then the negative flag bi...

Page 543: ...ointed to by loc16 loc16 loc16 XOR 16bit Smart Encoding If loc16 AH or AL and 16bit is an 8 bit number then the assembler will encode this instruction as XO RB AX 8bt To override this encoding use the...

Page 544: ...X AX XOR 0x00 8bit Flags and Modes N The load to AX is tested for a negative condition If bit 15 of AX is 1 then the negative flag bit is set otherwise it is cleared Z The load to AX is tested for a z...

Page 545: ...dress space 0x3F0000 to 0x3FFFFF On the C28x devices memory blocks are mapped to both program and data space unified memory hence the pma addressing mode can be used to access data space variables tha...

Page 546: ...ace 0x3F0000 to 0x3FFFFF On the C28x devices memory blocks are mapped to both program and data space unified memory hence the AL addressing mode can be used to access data space variables that fall wi...

Page 547: ...mits the program memory address to the high 64K of program address space 0x3F0000 to 0x3FFFFF On the C28x devices memory blocks are mapped to both program and data space unified memory hence the AL ad...

Page 548: ...ontrol only to a location located in the upper 64K range of program space 0x3F0000 to 0x3FFFFF To return from a call made by XCALL the XRET instruction must be used Flags and Modes V If the V flag is...

Page 549: ...escription Return conditionally If the specified condition is true a 16 bit value is popped from the stack and stored into the low 16 bits of the PC while the upper 6 bits of the PC are forced to 0x3F...

Page 550: ...VarB to zero and return This example only works for code located in upper 64K of program space XCALL FuncA Call FuncA FuncA Function A MOV AL VarA Load AL with contents of VarA XRETC NEQ Return if Var...

Page 551: ...o ACC is tested for a negative condition If bit 31 of ACC is 1 then the negative flag bit is set otherwise it is cleared Z The load to ACC is tested for a zero condition The zero flag bit is set if th...

Page 552: ...0 ST0 Flags and Modes OVC The 6 bit overflow counter bits OVC are cleared Repeat This instruction is not repeatable If this instruction follows the RPT instruction it resets the repeat counter RPTC an...

Page 553: ...e RPT instruction it resets the repeat counter RPTC and executes only once Example Calculate sum of product using 32 bit multiply and retain high result int32 X N Data information int32 C N Coefficien...

Page 554: ...ort with TI exten sions For more information about instructions shown in examples in this chapter see Chapter 6 Assembly Language Instructions Topic Page 7 1 Overview of Emulation Features 7 2 7 2 Deb...

Page 555: ...a software breakpoint instruction instruction replacement J Break on a specified program or data access without requiring instruc tion replacement accomplished using bus comparators J Break on externa...

Page 556: ...also requires a test clock return signal TCK_RET the target supply VCC and ground GND TCK_RET is a test clock out of the scan controller and into the target system The target system uses TCK_RET if it...

Page 557: ...t O I TRST Test reset O I I input O output Do not use pullup resistors on TRST it has an internal pulldown device In a low noise environment TRST can be left floating In a high noise environment an ad...

Page 558: ...This allows a C28x to power up in reset provided external hardware holds EMU0 low only while power up reset is active Yes Low High High Normal mode with emulation dis abled This is the setting that sh...

Page 559: ...which the device does not execute back ground code Time critical interrupt An interrupt that must be serviced even when background code is halted For example a time critical interrupt might service a...

Page 560: ...nalysis breakpoint watchpoint This state can also be entered by a re quest from the host processor In the stop mode debug halt state the CPU is halted You can place the device into one of the other tw...

Page 561: ...the contents of CPU registers and memory are not updated in the debugger display in the single instruction state or the run state Mask able interrupts occurring in any state are latched in the interr...

Page 562: ...d are always serviced once requested It is possible for multiple inter rupts to occur and be serviced while the device is in the debug halt state Suspending execution adds only one cycle to interrupt...

Page 563: ...upt processing began before the debug event occurred the debug event cannot be processed until the interrupt service routine begins Figure 7 3 illustrates the relationship among the three states Notic...

Page 564: ...ts subsequent occurrences of the interrupt from being ser viced until the IER is restored by a return from interrupt IRET instruction or until the interrupt is deliberately re enabled in the interrupt...

Page 565: ...gger command Run state Can service interrupts Can observe CPU Debugger command breakpoint or analysis stop After executing one instruction Debugger command Debugger command Debugger command Debugger c...

Page 566: ...ping Not serviced Maskable interrupt If running Serviced If stepping Latched in IFR but not serviced Run RS Serviced NMI Serviced Maskable interrupt Serviced Real time Debug halt RS Serviced NMI Servi...

Page 567: ...Modes 7 14 Note Unless you are using a real time operating system do not enable the real time operating system interrupt RTOSINT RTOSINT is completely dis abled when bit 15 in the IER is 0 and bit 15...

Page 568: ...s the original debug context will be restored The abort interrupt ABORTI instruction is provided as a means to indicate that the debug context will not be restored and the de bug logic needs to be res...

Page 569: ...DT DMA mechanism can operate in the following modes Nonpreemptive mode The DT DMA mechanism waits for a hole on the desired memory buses During the hole the DT DMA mechanism uses them to perform its r...

Page 570: ...This minimizes the intrusiveness of the debug access on a system Real time mode accesses are typically polite although there may be rea sons such as error recovery to perform rude accesses in real ti...

Page 571: ...by the IDLE instruction However unlike returning from an interrupt the CPU re turns to the idle state upon completion of the DT DMA Note The information shown on the debugger screen is gathered at di...

Page 572: ...software An analy sis breakpoint triggers a debug event when an instruction at a breakpoint ad dress would have entered the decode 2 phase of the pipeline this halts the CPU before the instruction is...

Page 573: ...nd data match the CPU stops with the IC pointing six instructions after that point MOV AR4 X MOV AL AR4 0 Data read nop nop nop nop nop nop The IC will point here In the following example a write addr...

Page 574: ...in address is not seen on the address bus within a certain number of CPU clock cycles a debug event occurs 7 7 4 Typical Analysis Unit Configurations Each analysis unit can be configured to perform on...

Page 575: ...only available with analysis unit 1 This counter can be used as a benchmark counter to count cycles or instructions It can also be used to count AU2 events Configuration of the analysis resources is...

Page 576: ...thing to receive the data 7 8 1 Creating a Data Logging Transfer Buffer To create a data logging transfer buffer follow these steps in your application code 1 Execute the EALLOW instruction to enable...

Page 577: ...and Table 7 5 on the following pages for descriptions of the registers associated with data logging Figure 7 6 ADDRL at Data Space Address 00 083816 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 16 LSBs of t...

Page 578: ...0 CPU nonpreemptive mode 1 Data logging preemptive mode 10 Allow data logging during time critical ISR 0 No 1 Yes 9 Allow data logging while DBGM 1 0 No polite accesses 1 Yes rude accesses 8 6 Set to...

Page 579: ...a logging operation has ended Bits 14 10 are corrupted when this occurs 00 084F16 EVT_ID R Data logging end address ID register 15 14 Resource control 0 Resource is free 1 Application owns resource 2...

Page 580: ...tion is not the owner then all of its writes are ignored 6 Disable writes to memory mapped emulation registers by executing the EDIS instruction If an interrupt occurs between the EALLOW instruction i...

Page 581: ...er base addr MOV AR4 DMA_CNTRL 1 Attempt to claim resource NOP NOP NOP CMP AR4 DMA_ID 7001h Value expected in ID register B FAIL NEQ If we don t see the correct ID then we failed the resource is alrea...

Page 582: ...empt to claim End Address MOV AR4 DMA_CNTRL 1 Attempt to claim Start Control NOP NOP NOP CMP AR5 EVT_ID 5002h Value expected in ID register B FAIL NEQ If we don t see the correct ID FAIL CMP AR4 DMA_I...

Page 583: ...the debugger the resources can be used even while the target system undergoes a reset Table 7 6 Analysis Resources Resource Purpose BA0 Break on contents of program address or memory address bus BA1...

Page 584: ...e attempt an operation that does not complete after a certain time out period as determined by the debug software it attempts to determine the probable cause and display the situa tion to you You can...

Page 585: ...This page intentionally left blank 7 32 This page intentionally left blank...

Page 586: ...ntrol registers of the 28x this appendix summarizes Their reset values The instructions available for accessing them The functions of their bits Topic Page A 1 Reset Values of and Instructions for Acc...

Page 587: ...t flag register 0000 0000 0000 00002 PUSH AND OR IER Interrupt enable register 0000 0000 0000 00002 MOV AND OR DBGIER Debug interrupt enable register 0000 0000 0000 00002 PUSH POP Note V Bit 3 of ST1...

Page 588: ...e value after reset Each unreserved bit field or set of bits has a callout that very briefly de scribes its effect on the processor Each nonreserved bit field or set of bits is labeled with one of the...

Page 589: ...1 1 1 R W R W R W R W R W R W Behaves differently for signed and unsigned operations Signed operations OVC Increments by 1 for each positive overflow Decrements by 1 for each negative overflow Unsigne...

Page 590: ...sing mode PAGE0 direct addressing mode 0 1 0 1 M0 and M1 mapping mode bit Auxiliary register pointer XAR0 selected XAR1 selected XAR2 selected XAR3 selected XAR4 selected XAR5 selected XAR6 selected X...

Page 591: ...E0 direct addressing mode 0 1 Interrupt vectors mapped to program memory addresses 00 000016 00 003F16 Interrupt vectors mapped to program memory addresses 3F FFC016 3F FFFF16 0 1 Vector map bit Stack...

Page 592: ...R W R W R W RTOSINT flag bit DLOGINT flag bit INT14 flag bit INT13 flag bit INT12 flag bit INT11 flag bit INT10 flag bit INT9 flag bit 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 INT8 INT7 INT6 INT5 INT4 INT3 INT...

Page 593: ...DLOGINT enable bit INT14 enable bit INT13 enable bit INT12 enable bit INT11 enable bit INT10 enable bit INT9 enable bit 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 INT8 INT7 INT6 INT5 INT4 INT3 INT2 INT1 R W 0 1...

Page 594: ...t INT14 debug enable bit INT13 debug enable bit INT12 debug enable bit INT11 debug enable bit INT10 debug enable bit INT9 debug enable bit 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 INT8 INT7 INT6 INT5 INT4 INT3...

Page 595: ...customized DSPs and describes the procedures for developing prototype and production units Information on sub mitting object code and on ordering customer ROM coded devices is also included Topic Page...

Page 596: ...e has been finalized the code can be submitted to Texas Instruments for masking into the on chip program ROM Figure B 1 illustrates the procedural flow for developing and ordering TMS320 masked parts...

Page 597: ...Customer submits custom code Customer submits device requirements Customer submits new code release form TI performs ROM receipt Customer approves ROM receipt No TI orders masks manufactures and ship...

Page 598: ...vice and progresses without gaps to the last address of the ROM and the addition of data in the reserved locations of the ROM for device ROM test Because these changes have been made a checksum compar...

Page 599: ...M Codes to TI B 3 ROM Layout 1K OTP ROM will be reserved for TI internal testing This space will follow the 1K OTP ROM meant for the customer Locations 0x3F7FF8 0x3F7FFF will contain the CSM passwords...

Page 600: ...d For example for DE121001 the decimal number 121001 will be converted to its hex adecimal equivalent 1D8A9 and stored in the D number locations D8A9 will be stored in address n and 0001 will be store...

Page 601: ...ocations see Table B 1 The image of the ROM is now ready in the PC memory Table B 1 Checksum Computation Memory Locations Address Content 0x3D7800 0x3D7BFB 1K OTP for customer code referred to in this...

Page 602: ...he start address for customer code in ROM depends on the part number While the start address is 0x3D8000 for C2812 C2811 it is 0x3E8000 for C2810 The customer code should provide a branch instruction...

Page 603: ...of the changes are listed here An emphasis is placed on those changes of which you need to be aware while migrating from a C2xLP based design to a C28x design In particular changes in CPU regis ters...

Page 604: ...ual MAC 32 bit register file 32 bit single cycle operations 4M linear program address reach 4G linear data address reach Dedicated software stack pointer Monitorless real time emulation 40 50 better C...

Page 605: ...he names on the right are the C28x names for the registers Figure C 1 Register Changes From C2xLP to C28x T or TH PH AH TL PL AL 9 AR0H AR0 AR1 AR1H AR2 AR2H AR3H AR3 AR4 AR4H AR6H AR7H AR5H AR6 AR7 A...

Page 606: ...C Return program counter The RPC register is new on the C28x When a call operation is performed the return address is saved in the RPC register and the old value in the RPC is saved on the stack When...

Page 607: ...ize The assembler linker automatically resolve the page value by dividing the absolute address of the specified location by 128 For example If VarA address 0x3456 then the DP value is DP 8 0 0x3456 12...

Page 608: ...DP and offset values as follows on the C28x C2xLP Original Source Mode v28 m20 mode AMODE 1 LDP VarA DP 15 0 0x3456 128 1 0x00D1 LACL VarA 7 bit offset 0x3456 0x007F 0x56 Equivalent C28x Mnemonics af...

Page 609: ...R W 0 R W 0 R W 0 Note R Read access W Write access value following dash is value after reset C2xLP Status Register ST1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ARB CNF TC SXM C 1 1 1 1 XF 1 1 PM R W X R...

Page 610: ...uctions correspond to equivalent C2xLP instructions conver sion On the C2xLP the PM bits corresponded to no shift at reset On C28x however the PM corresponds to a left shift of 1 at reset Table C 2 C2...

Page 611: ...tructions EALLOW Emulation access enable bit The EALLOW bit is new on the C28x It allows access to the emulation register on the C28x IDLESTAT IDLE status bit The IDLESTAT bit is new on the C28x It fl...

Page 612: ...conditions of internal registers have changed between the C2xLP and C28x as shown in Table C 4 Most C28x registers are cleared on a reset Differences in Table C 5 are highlighted in bold Table C 4 Res...

Page 613: ...2xLP Reset Value C28x Bit Name C28x Reset Value ST0 DP XXXXXXXXX SXM 0 INTM 1 OVM 0 OVM X TC 0 OV 0 C 0 ARP XXX Z 0 N 0 V 0 PM 000 left shift 1 ST1 PM 00 no shift INTM 1 XF 1 DBGM 1 C 1 PAGE0 0 SXM 1...

Page 614: ...non volatile memory at 0x3FFFC0 0x3FFFFF To take advantage of relocatable vectors or fetching vectors from fast internal memory space place the vectors at address 0x000000 0x00003F Often the C28x CPU...

Page 615: ...6 0x0000 0300 0x0000 0400 M1 SARAM 1K x 16 Emulation registers 2K x 16 0x0000 FFFF 0x001 0000 Reserved for only C28x addressing Memory Registers Vectors 32 x 32 enabled if VMAP 1 B2 Block B1 Block B0...

Page 616: ...the C28x for compatibility reasons and can only be accessed using IN and OUT UOUT instructions Not all C28x de vices will support I O space See the data sheet of your particular device for details Gl...

Page 617: ...on of a few instructions This chapter provides guidelines for C2xLP code migra tion to a C28x device C2xLP refers to the CPU used in all TMS320C24x TMS320C24xx and TMS320C20x DSP devices Topic Page D...

Page 618: ...xLP and C28x operating modes Future re leases of documents will contain code conversion examples and software li brary modules facilitating the conversion from C2xLP mixed C and assembly source to C28...

Page 619: ...ce memory map with C2xLP compatible memory sections Build a linker command file cmd See Table D 8 Select a C2xLP assembly source code asm for migration to C28x archi tecture 4 Boot Code Add the C2xLP...

Page 620: ...e initialization code segment to enable C2xLP compatible mode in the beginning of the code Step 5 Comment or fix incompatible instructions in C2xLP source if any Step 6 Invoke the C28x Assembler and a...

Page 621: ...elated errors 7 Assemble or reassemble using the C28x assembler until the assembly is successful with no errors The tables in section D 5 will help to resolve most of the errors during the assembly pr...

Page 622: ...roughout a source file For example if a file is assembled with the m20 option the assembler begins the assembly in the C28x object accept C2xLP syntax mode When it en counters the c28_amode directive...

Page 623: ...t SXM 0 for 28x at reset SETC C Carry bit 1 for C2xLP at reset Carry bit 0 for 28x at reset SPM 0 Set product shift mode zero that is PM bits 001 compatible to C2xLP PM reset mode D 4 2 IER IFR Code T...

Page 624: ...e IFR Register C2xLP C28x write 1 to clear SETC INTM LDP 0 SPLK 0FFFFh IFR CLRC INTM write 0 to clear AND IFR INTx operation is atomic and will not be interrupted D 4 3 Context Save Restore The C28x a...

Page 625: ...AR LAR AR7 LAR AR6 LAR AR5 LAR AR4 LAR AR3 LAR AR2 LAR AR0 SETC INTM MAR SPM 0 LT MPY 1 LT MAR LPH LACL ADD 16 LST 0 LST 1 CLRC INTM RET C28x automatically saves the following registers T ST0 AH AL PH...

Page 626: ...ter IFR Memory mapped register Write 1 to clear bits set in IFR IFR is a CPU register Write 0 to clear bits set in IFR 2 Interrupt enable register IMR Memory mapped register Renamed as IER and is a CP...

Page 627: ...ess 10 Context save No automatic context save See section D 3 for a full context save restore example Automatic context save of CPU regis ters T ST0 AH AL PH PL AR1 AR0 DP ST1 DBGSTAT IER PC See Table...

Page 628: ...and C28x Differences in Memory Maps Migration topic C2xLP C28x 1 Program memory 16 bit address Size 64kx16 Range 0x0000 0xFFFFh 22 bit address Size 64kx16 mapped to Range 0x3F 0000h 0x3F FFFFh 2 Data...

Page 629: ...0x0000 0xFFFFh Range 0x0x00 000 0x00 FFFFh I O Space may or may not be imple mented on a particular device See the device datasheet for details 6 Global space Range 0x8000 0xFFFFh Implemented via the...

Page 630: ...XAR1 0x10000h 6 2s complement subtraction to ARx LAR AR1 0FFFFh ADRK 0FE Result AR1 0xFFFDh MOV XAR1 0FFFFh ADD XAR1 0FE Result XAR1 0x1FFFDh 7 I O instructions Supports IN OUT instructions Supports I...

Page 631: ...rect addressing Auxiliary register will be pointed by ARP register in ST0 ARB is ARP pointer buffer in ST1 MAR AR2 ARP AR2 LACL No ARB equivalent in 28x Selected ARx is referenced in the in struction...

Page 632: ...ctal number 10 Order of precedence in ex pressions Syntax change Expressions in assembly state ments do not require parenthesis x set A B C D Expressions in assembly statements do require parenthesis...

Page 633: ...on the C28x The C28x assembler accepts both C28x and C2xLP as sembly source syntax This enables you to quickly port C2xLP code with mini mal effort Additionally all compatible C2xLP instructions have...

Page 634: ...Modes C2xLP Equivalent NEQ 0 ACC 0 EQ 0 ACC 0 GT 0 ACC 0 GEQ 0 ACC 0 LT 0 ACC 0 LEQ 0 ACC 0 HI higher HIS C higher or same carry set C 1 LO NC lower carry clear C 0 LOS lower or same NOV no overflow...

Page 635: ...lent Instructions C2xLP C28x Instruc tion Mnemonic Cycles Size Instruc tion Mnemonic Cycles Size ABS n 1 16 ABS ACC 1 16 ADD loc16 0 n 1 16 ADD ACC loc16 0 n 1 16 ADD loc16 1 15 n 1 16 ADD ACC loc16 1...

Page 636: ...of COND2 pma CONDn 7 48 BIT loc16 15 bit n 1 16 TBIT loc16 bit 1 16 BITT loc16 n 1 16 TBIT loc16 T 1 32 BLDD src_addr loc16 n 3 32 MOV loc16 0 src_addr n 2 32 BLDD loc16 dest_addr n 3 32 MOV 0 dest_a...

Page 637: ...32 INTR K 4 16 Not applicable LACC loc16 0 n 1 16 MOV ACC loc16 0 1 16 LACC loc16 1 15 n 1 16 MOV ACC loc16 1 15 1 32 LACC loc16 16 n 1 16 MOV ACC loc16 16 1 16 LACC 16bit 0 15 2 32 MOV ACC 16bit 0 15...

Page 638: ...MPY P T loc16 1 16 MPY 13bit 1 16 MPY P T 16bit 1 32 MPYA loc16 n l 16 MPYA P T loc16 n 1 16 MPYS loc16 n l 16 MPYS P T loc16 n 1 16 MPYU loc16 n l 16 MPYU P T loc16 1 16 NEG n l 16 NEG ACC 1 16 NMI 4...

Page 639: ...RPT 8bit 1 16 RPT 8bit 1 16 SACH loc16 0 n l 16 MOV loc16 AH n 1 16 SACH loc16 1 n l 16 MOVH loc16 ACC 1 n 1 16 SACH loc16 2 7 n l 16 MOVH loc16 ACC 2 7 n 1 32 SACL loc16 0 n l 16 MOV loc16 AL n 1 16...

Page 640: ...applicable SUB loc16 0 n l 16 SUB ACC loc16 0 n 1 16 SUB loc16 1 15 n l 16 SUB ACC loc16 1 15 n 1 32 SUB loc16 16 n l 16 SUB ACC loc16 16 n 1 16 SUB 8bit 1 16 SUBB ACC 8bit 1 16 SUB 16bit 0 15 2 32 S...

Page 641: ...C2xLP are repeatable on the C28x Table E 3 shows which C2xLP operations are repeatable and which ones are repeatable on the C28x Table E 3 Repeatable Instructions for the C2xLP and C28x C2xLP Instruc...

Page 642: ...peatable C28x Repeatable LACT mem X LAR AR mem X LDP mem X LPH mem X LST n mem X LT mem X LTA mem X X LTD mem X LTP mem X LTS mem X X MAC pma mem X X MACD pma mem X X MAR ind nextARP X X MPY mem X MPY...

Page 643: ...atable C28x Repeatable PSHD mem X PUSH X ROL X X ROR X X SACH mem shift X X SACL mem shift X X SAR AR mem X SETC CNF XF INTM OVM SXM TC C X SFL X X SFR X X SPAC X X SPH mem X X SPL mem X X SPLK lk mem...

Page 644: ...differences between the C27x and the C28x and describes how to migrate your code from a C27x based design to a C28x based design Topic Page F 1 Architecture Changes F 2 F 2 Moving to C28x Object F 9 F...

Page 645: ...ister modifications from the C27x are shown in Figure F 1 Shaded registers highlight the changes or enhancements for the C28x Figure F 1 C28x Registers T 16 IER 16 DBGIER 16 IFR 16 PC 22 AR7 16 AR6 16...

Page 646: ...it operations The net result is that return operations are faster 4 instead of 8 cycles SP 16 By default the C28x SP register is initialized to 0x400 after a reset ST0 16 Shaded items indicate a chang...

Page 647: ...bit as 0 OBJMODE This mode is used to select between C27x object mode OBJMODE 0 and C28x object mode OBJMODE 1 compatibility This bit is set by the C28OBJ or SETC OBJMODE instructions This bit is cle...

Page 648: ...trap operation and automatically restored on an IRET instruction Figure F 2 Full Context Save Restore 31 16 1 0 T ST0 AH AL PH PL AR1 AR0 DP ST1 DBGSTAT IER PCH PCL Due to the register changes descri...

Page 649: ...cles pop XAR7 pop XAR6 pop AR5 AR4 pop AR3 AR2 iret 12 cycles If you perform a task switch operation stack changes the RPC register must be manually saved You are not to save the RPC register if the s...

Page 650: ...the M0M1MAP bit in status register 1 ST1 to a 0 Executing the C27MAP or CLRC M0M1MAP instruction is the only way to clear this bit With M0M1MAP 0 the mapping is compatible with the C27x B0 and B1 blo...

Page 651: ...only assumes OBJMODE 0 Once you have taken the mapping of blocks M0 and M1 into account as previously described you can simply load the C27x object out code into the C28x and run it When using the C2...

Page 652: ...ndow in the debugger may display incorrect information This is because the debugger will decode memory as C27x opcodes until after you execute the C28OBJ instruction When running in this mode the disa...

Page 653: ...ro values You MUST zero out the upper bits of the XARn registers when switching from OBJMODE 1 to OBJMODE 0 It is recommended that you not switch modes frequently in your code Typically you will selec...

Page 654: ...our C27x code to pure C28x code F 3 1 Instruction Syntax Changes Syntax changes were necessary for clarity and because of changes in the aux iliary registers stretched pointers Table F 3 shows the C27...

Page 655: ...VL XAR6 7 22bit MOV loc32 XAR6 7 MOVL loc32 XAR6 7 MOVL loc32 XAR6 7 CALL 22bit LC 22bit LC 22bit CALL XAR7 LC XAR7 LC XAR7 RET LRET LRET RETE LRETE LRETE MOV ACC P MOVP T T decode MOVL ACC P PM MOVP...

Page 656: ...atable The follow ing two tables list those instructions that are repeatable on the C28x device These instructions are repeatable in both C27x compatible mode OBJMODE 0 and C28x native mode OBJMODE 1...

Page 657: ...truction changed slightly from the C27x to the C28x Under the prescribed usage of the SUBCU operation the change will yield the same result as the C27x The SUBCU instruction operates as follows on the...

Page 658: ...ration is complete The operation of the C N Z flags should be identical to the C27x implementa tion The V flag and overflow counter OVC are not affected by the operation On the C27x the V and OVC flag...

Page 659: ...ode to C28x native instructions you will no longer use the m27 switch to allow for C27x source as shown in Figure F 8 Figure F 8 Compiling C28x Source CL2000 V28 C28x Source Code asm c cpp C28x Object...

Page 660: ...ough 16 AL bits 15 through 0 AH MSB bits 31 through 24 AH LSB bits 23 through 16 AL MSB bits 15 through 8 and AL LSB bits 7 through 0 address generation logic Hardware in the CPU that generates the ad...

Page 661: ...properly en abled If the interrupt is nonmaskable the CPU approves the request im mediately See also interrupt request and service an interrupt ARAU See address register arithmetic unit ARAU arithmet...

Page 662: ...ister B background code The body of code that can be halted during debugging because it is not time critical barrel shifter Hardware in the CPU that performs all left and right shifts of register or d...

Page 663: ...e block of code or data that ultimately occupies a space adjacent to other blocks of code in the memory map conditional branch instruction A branch instruction that may or may not cause a branch depen...

Page 664: ...data program write data bus DWDB The bus that carries data during writes to data space or program space data read address bus DRAB The bus that carries addresses for reads from data space data read da...

Page 665: ...sta tus information This register which need not be read from or written to is saved and restored during interrupt servicing to preserve the debug context during debugging decode an instruction To id...

Page 666: ...AB See data write address bus DWAB DWDB See data program write data bus DWDB E E phase See execute E phase EALLOW bit See emulation access enable EALLOW bit EMU0 and EMU1 pins Pins known as the TI ext...

Page 667: ...ad dress of the instruction s to be fetched See also pipeline phases fetch 2 F2 phase The second of eight pipeline phases an instruction passes through In this phase the CPU fetches an instruction or...

Page 668: ...illegal instruction trap A trap that is serviced when an illegal instruction is decoded immediate address An address that is specified directly in an instruction as a constant immediate addressing mo...

Page 669: ...struction but there are no in structions waiting in the instruction fetch queue This condition causes the decode 2 through write phases of the pipeline to freeze until one or more new instructions hav...

Page 670: ...the interrupt must be enabled in the IER and in the DBGIER debug interrupt enable regis ter interrupt priority See hardware interrupt priority interrupt request A signal or instruction that requests t...

Page 671: ...n interrupt is latched when its flag bit has been latched in the interrupt flag register IFR least significant bit LSB The bit in the lowest position of a binary number For example the LSB of a 16 bit...

Page 672: ...me physical memory block as another range of addresses most significant bit MSB The bit in the highest position of a binary num ber For example the MSB of a 16 bit register value is bit 15 See also LS...

Page 673: ...n in struction Thus an opcode includes the binary sequence for the instruc tion type and the binary sequence and or constant in which the operands are encoded operand This document uses operand to mea...

Page 674: ...lets ACC overflow normally but keeps track of each overflow by incrementing or decrement ing by 1 the overflow counter OVC in ST0 P P register See product register P PAB See program address bus PAB P...

Page 675: ...wo decoupled por tions of the pipeline Freezes in the fetch 1 through decode 1 portion of the pipeline are caused by a not ready signal from program memory Freezes in the decode 2 through write portio...

Page 676: ...these instructions and passes commands and constant data to other parts of the CPU program counter PC When the pipeline is full the 22 bit PC always points to the instruction that is currently being p...

Page 677: ...elated decode mechanism are much simpler than those of mi croprogrammed complex instruction set computers register addressing mode An addressing mode that enables you to refer ence registers by name r...

Page 678: ...or peripheral devices for particular types of read and write operations scan controller A device that performs JTAG state sequences sent to it by a host processor These sequences in turn control the...

Page 679: ...ion has forced the SP to align to the next even address SPA 1 stack pointer indirect addressing mode The indirect addressing mode that references a data memory value at the current position of the sta...

Page 680: ...rol flag TC A bit in status register ST0 that shows the result of a test performed by the TBIT test bit instruction or the NORM normal ize instruction test logic reset A test and emulation logic condi...

Page 681: ...state A cycle during which the CPU waits for a memory or peripheral device to be ready for a read or write operation watchpoint A place in a routine where it is to be halted if an address or an addres...

Page 682: ...DDL loc32 ACC 6 38 address buses 1 9 address counters FC IC and PC 4 5 address maps 1 8 address reach C 5 address register arithmetic unit ARAU 1 5 2 2 addressing modes 5 1 5 2 byte 5 31 direct 2 10 d...

Page 683: ...34 carry C 2 25 debug enable mask DBGM 2 37 debug interrupt enable register DBGIER 3 10 emulation access enable EALLOW 2 35 IDLE status IDLESTAT 2 35 interrupt enable register IER 3 9 interrupt flag r...

Page 684: ...AP 6 68 CLRC OBJMODE 6 69 CLRC OVC 6 70 CLRC XF 6 71 CLRC mode 6 72 CMP AX loc16 6 74 CMP loc16 16bitSigned 6 75 CMP64 ACC P 6 77 CMPB AX 8bit 6 79 CMPL ACC loc32 6 80 CMPL ACC P PM 6 81 CMPR 0 6 82 c...

Page 685: ...8 pipeline conflict 4 13 4 14 relationship between pipeline and address count ers 4 6 shift operations 2 45 T320C28x DSP core 1 4 DINT 6 85 Direct Addressing Mode 5 2 5 8 direct addressing mode C 5 Di...

Page 686: ...e mode 7 5 I I O space C 14 IACK 16bit 6 97 IC instruction counter 4 5 IDLE 6 98 IDLE status bit IDLESTAT 2 35 IDLESTAT C 9 IDLESTAT bit 2 35 IEEE 1149 1 JTAG signals 7 3 IER A 2 IFR A 2 illegal instr...

Page 687: ...stant 6 164 MOV loc16 OVC store the overflow counter 6 173 MOV OVC loc16 load the overflow counter 6 176 MOV 0 16bit loc16 move value 6 156 OR ACC loc16 bitwise OR 6 257 OUT PA loc16 output data to po...

Page 688: ...JTAG port 7 1 L LACL dma D 15 LB XAR7 6 119 LB 22bit 6 120 LC XAR7 6 121 LC 22bit 6 122 LCR 22bit 6 123 LCR XARn 6 124 load auxiliary register 6 160 load AX 6 161 load data page pointer 6 162 load the...

Page 689: ...MOV DP 10bit 6 162 MOV IER loc16 6 163 MOV loc16 0 6 166 MOV loc16 16bit 6 164 MOV loc16 0 16bit 6 165 MOV loc16 AX 6 169 MOV loc16 AX COND 6 170 MOV loc16 IER 6 172 MOV loc16 OVC 6 173 MOV loc16 P 6...

Page 690: ...n 6 250 NORM ACC ind 6 251 NORM ACC XARn 6 253 normal mode 7 5 NOT ACC 6 255 NOT AX 6 256 O OBJMODE C 9 F 4 F 9 OBJMODE bit 1 2 operating modes selecting by using TRST EMU0 and EMU1 7 5 operations mul...

Page 691: ...nter C 4 program counter D 14 program counter PC 2 14 4 5 program flow 2 39 Program space C 12 program space address map 1 8 program space read and write 1 10 program address counters 4 5 program read...

Page 692: ...ister ST1 2 14 2 34 T register 2 8 registers after reset 3 23 repeat counter RPTC 2 39 repeat instructions D 13 repeatable instructions E 9 F 13 reserved addresses 1 8 Reserved memory C 14 reset 1 3 r...

Page 693: ...ST1 Register Bits table F 4 stack 2 11 Stack Addressing Mode 5 2 5 9 Stack Pointer C 4 stack pointer SP 2 11 Stack pointer alignment bit C 9 stack pointer alignment bit SPA 2 36 Stack space C 14 star...

Page 694: ...rol flag TC C 10 test control flag bit TC 2 30 testing and debugging signals 1 6 TI internal testing B 5 time critical interrupts definition 7 6 serviced in real time mode 7 9 TMS signal 7 4 TMS320C20...

Page 695: ...ma 6 378 XMACD P loc16 pma 6 380 XOR AX loc16 6 384 XOR ACC 16bit 0 15 6 383 XOR ACC loc16 6 382 XOR loc16 AX 6 385 XOR loc16 16bit 6 386 XORB AX 8bit 6 387 XPREAD loc16 pma 6 388 XPREAD loc16 AL 6 38...

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