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Register Figures
Figure A
−
1. Status register ST0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
ÉÉÉ
ÉÉÉ
ÉÉÉ
0
0
0
0
0
0
0
0
0
0
0
OVC/OVCU
PM
V
N
Z
C
TC
OVM SXM
Overflow counter
R/W
R/W
Flag is reset
Overflow detected
0
1
Overflow flag
R/W
Sign extension suppressed
Sign extension mode selected
0
1
Sign-extension mode
Product shift mode
Left shift by 1
No shift
Right shift by 1, sign extended
Right shift by 2, sign extended
Right shift by 3, sign extended
Right shift by 4, sign extended
Right shift by 5, sign extended
Right shift by 6, sign extended
0
0
1
1
0
0
1
1
0
0
0
0
1
1
1
1
R/W
R/W
R/W
R/W
R/W
R/W
Behaves differently for signed and unsigned
operations:
Signed operations (OVC)
Increments by 1 for each positive overflow;
Decrements by 1 for each negative overflow.
Unsigned operations (OVCU)
Increments by 1 for ADD operations that
generate a Carry
Decrements by 1 for SUB operations that
generate a Borrow
0
1
0
1
0
1
0
1
Negative condition false
Negative condition true
0
1
Negative flag
Zero condition false
Zero condition true
0
1
Zero flag
Carry not detected/borrow detected
Carry detected/borrow not detected
0
1
Carry bit
Holds result of test performed
by TBIT or NORM instruction
Test/control flag
Results overflow normally
Overflow mode selected
0
1
ACC overflow mode
Note:
Summary of Contents for TMS320C28x
Page 30: ...1 12...
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Page 269: ...IN loc16 PA 6 112 MOV AL 0 AL 0 UOUT IORegC AL IOspace IORegC AL 10...
Page 308: ...MAXCUL P loc32 6 151 Saturate MOVL Var64 2 ACC Store result into Var64 MOVL Var64 P...
Page 509: ...SUBL ACC P PM 6 352 SUBL ACC P PM ACC S B 11 M X 4 MOVH Y ACC 5 Store Q15 result into Y...
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