Texas Instruments TMS320C28x, Reference Manual

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Data Logging
7-27 Emulation Features
3) Wait at least three cycles so that the write to the control register (done in
the write phase of the pipeline) occurs before the read from the ID register
in step 4. You can fill in the extra cycles with NOP (no operation) instruc-
tions or with other instructions that do not involve accessing the emulation
registers.
4) Read the appropriate ID register and verify that the application is the own-
er. The resource for data logging transfers uses DMA_ID (see Table 7 − 4
on page 7-25). The resource for detecting the data logging end address
uses EVT_ID (see Table 7
− 5 on page 7-26). If the application is not the
owner, then go back to step 2 until this succeeds (you may want a time-out
function to prevent an endless loop). This step is optional. The application
would fail to become the owner only if the debugger already owns the re-
source.
5) If the application is the owner, the remaining registers for that function can
be programmed, and the control register written to again, to enable the
function. However, if the application is not the owner, then all of its writes
are ignored.
6) Disable writes to memory-mapped emulation registers by executing the
EDIS instruction.
If an interrupt occurs between the EALLOW instruction in step 1 and the EDIS
instruction in step 6, access to emulation registers are automatically disabled
by the CPU before the interrupt service routine begins and automatically reen-
abled when the CPU returns from the interrupt. This means that there is no
need to disable interrupts between the EALLOW instruction and the EDIS in-
struction.
The debugger can, at your request, seize ownership of a register from the ap-
plication; however, that is not the normal mode of operation.
7.8.3 Data Log Interrupt (DLOGINT)
The completion of a data logging transfer (determined either by the word
counter or by the end address) triggers a DLOGINT request. DLOGINT is ser-
viced only if it is properly enabled. If the CPU is halted in real-time mode, DLO-
GINT must be enabled in both the DBGIER and the IER. Otherwise, DLOGINT
must be enabled in the IER and by the INTM bit in status register ST1.
This interrupt capability is most useful when there are multiple buffers of data
to be transferred through data logging and the completion of one transfer
should begin the next.