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CPU Registers
2-11
Central Processing Unit
Figure 2
−
6. Pages of Data Memory
11 1111 1111 1111 11
11 1111
11 1111
00 0000 0000 0000 10
00 0000 0000 0000 01
00 0000 0000 0000 10
00 0000 0000 0000 00
Data memory
Page 0:
Page 1:
Page 2:
Page 65
535:
00 0000
Offset
Data page
00 0000 0000 0000 00
11 1111
00 0000 0000 0000 01
11 1111 1111 1111 11
00 0000
00 0000
11 1111
00 0000
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0000
0000
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0000
003F
0000
0040
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0000
007F
0000
0080
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0000
00BF
003F
FFC0
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003F
FFFF
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Data memory above 4M words is not accessible using the DP.
When operating in C2xLP source-compatible mode, a 7-bit offset is used and
the least significant bit of the DP register is ignored. See Appendix C for more
details.
2.2.5 Stack Pointer (SP)
The stack pointer (SP) enables the use of a software stack in data memory.
The stack pointer has only 16 bits and can only address the low 64K of data
space (see Figure 2
7). When the SP is used, the upper six bits of the 32-bit
address are forced to 0. (For information about addressing modes that use the
SP, see section 5.5 on page 5-9.). After reset, SP points to address
0000
0400
16
.
Summary of Contents for TMS320C28x
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Page 269: ...IN loc16 PA 6 112 MOV AL 0 AL 0 UOUT IORegC AL IOspace IORegC AL 10...
Page 308: ...MAXCUL P loc32 6 151 Saturate MOVL Var64 2 ACC Store result into Var64 MOVL Var64 P...
Page 509: ...SUBL ACC P PM 6 352 SUBL ACC P PM ACC S B 11 M X 4 MOVH Y ACC 5 Store Q15 result into Y...
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