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Code Examples
Table D
−
3. Code to Enable an Interrupt
C2xLP
C28x
SETC
INTM
LDP
#0
LACL
IMR
OR
#INTx
SACL
IMR
CLRC
INTM
OR
IER,#INTx
;operation is atomic and
;will not be interrupted.
Table D
−
4. Code to Clear the IFR Register
C2xLP
C28x
;write 1 to clear
SETC
INTM
LDP
#0
SPLK
#0FFFFh,IFR
CLRC
INTM
;write 0 to clear
AND
IFR,#~INTx
;operation is atomic and
;will not be interrupted
D.4.3 Context Save/Restore
The C28x automatically saves a number of registers on each interrupt. To per-
form a full context save, some additional code must be added. Table D
shows a typical full context save and restore for both processors.
Summary of Contents for TMS320C28x
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Page 269: ...IN loc16 PA 6 112 MOV AL 0 AL 0 UOUT IORegC AL IOspace IORegC AL 10...
Page 308: ...MAXCUL P loc32 6 151 Saturate MOVL Var64 2 ACC Store result into Var64 MOVL Var64 P...
Page 509: ...SUBL ACC P PM 6 352 SUBL ACC P PM ACC S B 11 M X 4 MOVH Y ACC 5 Store Q15 result into Y...
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