Texas Instruments TMS320C28x, Reference Manual

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Pipelining of Instructions
4-4
Although every instruction passes through the eight phases, not every phase
is active for a given instruction. Some instructions complete their operations
in the decode 2 phase, others in the execute phase, and still others in the write
phase. For example, instructions that do not read from memory perform no
operations in the read phases, and instructions that do not write to memory
perform no operation in the write phase.
Because different instructions perform modifications to memory and registers
during different phases of their completion, an unprotected pipeline could lead
to reads and writes at the same location happening out of the intended order.
The CPU automatically adds inactive cycles to ensure that these reads and
writes happen as intended. For more details about pipeline protection, see
section 4.4 on page 4-12.
4.1.1 Decoupled Pipeline Segments
The fetch 1 through decode 1 (F1 − D1) hardware acts independently of the
decode 2 through write (D2 − W) hardware. This allows the CPU to continue
fetching instructions when the D2 − W phases are halted. It also allows fetched
instructions to continue through their D2 − W phases when fetching of new
instructions is delayed. Events that cause portions of the pipeline to halt are
described in section 4.3.
Instructions in their fetch 1, fetch 2, and decode 1 phases are discarded if an
interrupt or other program-flow discontinuity occurs. An instruction that reach-
es its decode 2 phase always runs to completion before any program-flow
discontinuity is taken.
4.1.2 Instruction-Fetch Mechanism
Certain branch instructions perform prefetching. The first few instructions of
the branch destination will be fetched but not allowed to reach DZ until it is
known whether the discontinuity will be taken. The instruction-fetch mecha-
nism is the hardware for the F1 and F2 pipeline phases. During the F1 phase,
the mechanism drives an address on the program address bus (PAB). During
the F2 phase, it reads from the program-read data bus (PRDB). While an
instruction is read from program memory in the F2 phase, the address for the
next fetch is placed on the program address bus (during the next F1 phase).
The instruction-fetch mechanism contains an instruction-fetch queue of four
32-bit registers. During the F2 phase, the fetched instruction is added to the
queue, which behaves like a first-in, first-out (FIFO) buffer. The first instruction
in the queue is the first to be executed. The instruction-fetch mechanism per-
forms 32-bit fetches until the queue is full. When a program-flow discontinuity