Texas Instruments TMS320C28x, Reference Manual

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Maskable Interrupts: INT1 − INT14, DLOGINT, and RTOSINT
3-6
3.3 Maskable Interrupts: INT1 − INT14, DLOGINT, and RTOSINT
INT1 − INT14 are 14 general-purpose interrupts. DLOGINT (the data log inter-
rupt) and RTOSINT (the real-time operating system interrupt) are available for
emulation purposes. These interrupts are supported by three dedicated regis-
ters: the CPU interrupt flag register (IFR), the CPU interrupt enable register
(IER), and the CPU debug interrupt enable register (DBGIER).
The 16-bit IFR contains flag bits that indicate which of the corresponding inter-
rupts are pending (waiting for approval from the CPU). The external input lines
INT1
− INT14 are sampled at every CPU clock cycle. If an interrupt signal is rec-
ognized, the corresponding bit in the IFR is set and latched. For DLOGINT or
RTOSINT, a signal sent by the CPU on-chip analysis logic causes the corre-
sponding flag bit to be set and latched. You can set one or more of the IFR bits
at the same time by using the OR IFR instruction. More details about the IFR
are given in section 3.3.1. The on-chip analysis resources are introduced in
Chapter 7.
The interrupt enable register (IER) and the debug interrupt enable register
(DBGIER) each contain bits for individually enabling or disabling the maskable
interrupts. To enable one of the interrupts in the IER, you set the corresponding
bit in the IER; to enable the same interrupt in the DBGIER, you set the corre-
sponding bit in the DBGIER. The DBGIER indicates which interrupts can be
serviced when the CPU is in the real-time emulation mode. The IER and the
DBGIER are discussed more in section 3.3.2. Real-time mode is discussed in
section 7.4.2 on page 7-9.
The maskable interrupts also share bit 0 in status register ST1. This bit, the
interrupt global mask bit (INTM), is used to globally enable or globally disable
these interrupts. When INTM = 0, these interrupts are globally enabled. When
INTM = 1, these interrupts are globally disabled. You can set and clear INTM
with the SETC INTM and CLRC INTM instructions, respectively. ST1 is de-
scribed in section 2.4 on page 2-34.
After a flag has been latched in the IFR, the corresponding interrupt is not serv-
iced until it is appropriately enabled by two of the following: the IER, the
DBGIER, and the INTM bit. As shown in Table 3
− 2, the requirements for enab-
ling the maskable interrupts depend on the interrupt-handling process used.
In the standard process, which occurs in most circumstances, the DBGIER is
ignored. When the C28x is in real-time emulation mode and the CPU is halted,
a different process is used. In this special case, the DBGIER is used and the
INTM bit is ignored. (If the DSP is in real-time mode and the CPU is running,
the standard interrupt-handling process applies.)