Texas Instruments TMS320C28x, Reference Manual

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CPU Interrupts Overview
3-2
3.1 CPU Interrupts Overview
Interrupts are hardware- or software-driven signals that cause the C28x CPU
to suspend its current program sequence and execute a subroutine. Typically,
interrupts are generated by peripherals or hardware devices that need to give
data to or take data from the C28x (for example, A/D and D/A converters and
other processors). Interrupts can also signal that a particular event has taken
place (for example, a timer has finished counting).
On the C28x, interrupts can be triggered by software (the INTR, OR IFR, or
TRAP instruction) or by hardware (a pin, an external peripheral, or on-chip
peripheral/logic). If hardware interrupts are triggered at the same time, the
C28x services them according to a set priority ranking.
Some 28x devices include a peripheral interrupt expansion (PIE) module that
multiplexes interrupts from a number of peripherals into a single CPU interrupt.
The PIE module provides additional control before an interrupt reaches the
C28x CPU. See the
TMS320C8x System and Interrupts Reference Guide
(literature number SPRU078) for more details.
At the CPU level, each of the C28x interrupts, whether hardware or software,
can be placed in one of the following two categories:
-
Maskable interrupts. These are interrupts that can be blocked (masked)
or enabled (unmasked) through software.
-
Nonmaskable interrupts. These interrupts cannot be blocked. The C28x
will immediately approve this type of interrupt and branch to the corre-
sponding subroutine. All software-initiated interrupts are in this category.
The C28x handles interrupts in four main phases:
1) Receive the interrupt request. Suspension of the current program se-
quence must be requested by a software interrupt (from program code) or
a hardware interrupt (from a pin or an on-chip device).
2) Approve the interrupt. The C28x must approve the interrupt request. If
the interrupt is maskable, certain conditions must be met in order for the
C28x to approve it. For nonmaskable hardware interrupts and for software
interrupts, approval is immediate.
3) Prepare for the interrupt service routine and save register values.
The main tasks performed in this phase are:
-
Complete execution of the current instruction and flush from the pipe-
line any instructions that have not reached the decode 2 phase.
-
Automatically save most of the current program context by saving the
following registers to the stack: ST0, T, AL, AH, PL, PH, AR0, AR1, DP,
ST1, DBGSTAT, PC, and IER.