Texas Instruments MSP430x4xx Family, User Manual

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USCI Operation: I2C Mode
21-21 Universal Serial Communication Interface, I2C Mode
21.3.5 I
2
C Clock Generation and Synchronization
The I
2
C clock SCL is provided by the master on the I
2
C bus. When the USCI
is in master mode, BITCLK is provided by the USCI bit clock generator and the
clock source is selected with the UCSSELx bits. In slave mode the bit clock
generator is not used and the UCSSELx bits are don’t care.
The 16-bit value of UCBRx in registers UCBxBR1 and UCBxBR0 is the division
factor of the USCI clock source, BRCLK. The maximum bit clock that can be
used in single master mode is f
BRCLK
/4. In multi-master mode the maximum
bit clock is f
BRCLK
/8. The BITCLK frequency is given by:
f
BitClock
+
f
BRCLK
UCBRx
The minimum high and low periods of the generated SCL are
t
LOW,MIN
+
t
HIGH,MIN
+
UCBRx
ń
2
f
BRCLK
when UCBRx is even and
t
LOW,MIN
+
t
HIGH,MIN
+
(UCBRx
*
1)
ń
2
f
BRCLK
when UCBRx is odd.
The USCI clock source frequency and the prescaler setting UCBRx must to
be chosen such that the minimum low and high period times of the I
2
C specifi-
cation are met.
During the arbitration procedure the clocks from the different masters must be
synchronized. A device that first generates a low period on SCL overrules the
other devices forcing them to start their own low periods. SCL is then held low
by the device with the longest low period. The other devices must wait for SCL
to be released before starting their high periods. Figure 21−16 illustrates the
clock synchronization. This allows a slow slave to slow down a fast master.
Figure 21−16. Synchronization of Two I
2
C Clock Generators During Arbitration
Wait
State
Start HIGH
Period
SCL From
Device #1
SCL From
Device #2
Bus Line
SCL