Timer_B Operation
16-7
Timer_B
Continuous Mode
In continuous mode the timer repeatedly counts up to TBR
(max)
and restarts
from zero as shown in Figure 16−4. The compare latch TBCL0 works the same
way as the other capture/compare registers.
Figure 16−4. Continuous Mode
0h
TBR(max)
The TBIFG interrupt flag is set when the timer counts from TBR
(max)
to zero.
Figure 16−5 shows the flag set cycle.
Figure 16−5. Continuous Mode Flag Setting
TBR (max)−1 TBR (max)
0h
Timer Clock
Timer
Set TBIFG
1h
TBR (max)
0h
TBR (max)−1
Summary of Contents for MSP430x4xx Family
Page 1: ...MSP430x4xx Family 2007 Mixed Signal Products User s Guide SLAU056G ...
Page 2: ......
Page 6: ...vi ...
Page 114: ...3 76 RISC 16 Bit CPU ...
Page 304: ...5 20 FLL Clock Module ...
Page 340: ...7 8 Supply Voltage Supervisor ...
Page 348: ...8 8 16 Bit Hardware Multiplier ...
Page 372: ...9 24 32 Bit Hardware Multiplier ...
Page 400: ...10 28 DMA Controller ...
Page 428: ...13 10 Basic Timer1 ...
Page 466: ...15 24 Timer_A ...
Page 522: ...17 30 USART Peripheral Interface UART Mode ...
Page 544: ...18 22 USART Peripheral Interface SPI Mode ...
Page 672: ...23 12 Comparator_A ...
Page 692: ...24 20 LCD Controller ...
Page 746: ...26 28 ADC12 ...