Texas Instruments MSP430x4xx Family, User Manual

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USCI Operation: UART Mode
19-20 Universal Serial Communication Interface, UART Mode
19.3.12 Receive Bit Timing
Receive timing error consists of two error sources. The first is the bit-to-bit
timing error similar to the transmit bit timing error. The second is the error
between a start edge occurring and the start edge being accepted by the USCI
module. Figure 19−11 shows the asynchronous timing errors between data on
the UCAxRXD pin and the internal baud-rate clock. This results in an additional
synchronization error. The synchronization error t
SYNC
is between
−0.5 BRCLKs and +0.5 BRCLKs, independent of the selected baud rate
generation mode.
Figure 19−11.Receive Error
1 2 3 4 5 6
0 i
t
0
t
ideal
7 8
1
t
1
2
9 10 11 12 13 14 1 2 3 4 5 6 7 8 9 10 11 12 13 14 1 2 3 4 5 6 7
t
0
t
1
t
2
ST D0 D1
D0 D1
ST
Synchronization Error
±
0.5x BRCLK
Majority Vote Taken Majority Vote Taken Majority Vote Taken
BRCLK
UCAxRXD
RXD synch.
t
actual
Sample
RXD synch.
The ideal sampling time t
bit,ideal,RX
[i] is in the middle of a bit period:
t
bit,ideal,RX
[i]
+
1
Baudrate
(
i
)
0.5
)
The real sampling time t
bit,RX
[i] is equal to the sum of all previous bits according
to the formulas shown in the transmit timing section, plus one half BITCLK for
the current bit i, plus the synchronization error t
SYNC
.
This results in the following t
bit,RX
[i] for the low-frequency baud rate mode
t
bit,RX
[i]
+
t
SYNC
)
ȍ
i
*
1
j
+
0
T
bit,RX
[j]
)
1
f
BRCLK
ǒ
INT(1
2
UCBRx)
)
m
UCBRSx
[i]
Ǔ
where:
T
bit,RX
[i]
+
1
f
BRCLK
ǒ
UCBRx
)
m
UCBRSx
[i]
Ǔ
m
UCBRSx
[i]: Modulation of bit i from Table 19−2