Texas Instruments MSP430x4xx Family, User Manual

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DMA Registers
10-25 DMA Controller
DMAxDA, DMA Destination Address Register
31 30 29 28 27 26 25 824
Reserved
r0 r0 r0 r0 r0 r0 r0 r0
23 22 21 20 19 18 17 16
Reserved DMAxDAx
r0 r0 r0 r0 rw rw rw rw
15 14 13 12 11 10 9 8
DMAxDAx
rw rw rw rw rw rw rw rw
7 6 5 4 3 2 1 0
DMAxDAx
rw rw rw rw rw rw rw rw
Reserved Bits
31−20 Reserved
DMAxDAx Bits
19−0 DMA destination address. The destination address register points to the
destination address for single transfers or the first address for block transfers.
The DMAxDA register remains unchanged during block and burst-block
transfers.
Devices that have addressable memory range 64−KB or below contain a
single word for the DMAxDA.
MSP430FG461x devices implement two words for the DMAxDA register as
shown. Bits 31−20 are reserved and always read as zero. Reading or writing
bits 19-16 requires the use of extended instructions. When writing to
DMAxDA with word instructions, bits 19-16 are cleared.