Texas Instruments MSP430x4xx Family, User Manual

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USCI Operation: UART Mode
19-14 Universal Serial Communication Interface, UART Mode
error flags except UCOE if UCAxRXBUF was overwritten between the read
access to UCAxSTAT and to UCAxRXBUF. So the UCOE flag should be
checked after reading UCAxRXBUF to detect this condition. Note, in this case
the UCRXERR flag is not set.
19.3.7 USCI Receive Enable
The USCI module is enabled by clearing the UCSWRST bit and the receiver
is ready and in an idle state. The receive baud rate generator is in a ready state
but is not clocked nor producing any clocks.
The falling edge of the start bit enables the baud rate generator and the UART
state machine checks for a valid start bit. If no valid start bit is detected the
UART state machine returns to its idle state and the baud rate generator is
turned off again. If a valid start bit is detected a character will be received.
When the idle-line multiprocessor mode is selected with UCMODEx = 01 the
UART state machine checks for an idle line after receiving a character. If a start
bit is detected another character is received. Otherwise the UCIDLE flag is set
after 10 ones are received and the UART state machine returns to its idle state
and the baud rate generator is turned off.
Receive Data Glitch Suppression
Glitch suppression prevents the USCI from being accidentally started. Any
glitch on UCAxRXD shorter than the deglitch time t
τ
(approximately 150 ns)
will be ignored by the USCI and further action will be initiated as shown in
Figure 19−8. See the device-specific data sheet for parameters.
Figure 19−8. Glitch Suppression, USCI Receive Not Started
URXDx
URXS
t
τ
When a glitch is longer than
t
τ,
or a valid start bit occurs on UCAxRXD, the
USCI receive operation is started and a majority vote is taken as shown in
Figure 19−9. If the majority vote fails to detect a start bit the USCI halts
character reception.