Basic Timer1 Introduction
13-7
Basic Timer1
BTCTL, Basic Timer1 Control Register
7
6
5
4
3
2
1
0
BTSSEL
BTHOLD
BTDIV
BTFRFQx
BTIPx
rw
rw
rw
rw
rw
rw
rw
rw
BTSSEL
Bit 7
BTCNT2 clock select. This bit, together with the BTDIV bit, selects the
clock source for BTCNT2. See the description for BTDIV.
BTHOLD
Bit 6
Basic Timer1 Hold.
0
BTCNT1 and BTCNT2 are operational
1
BTCNT1 is held if BTDIV=1
BTCNT2 is held
BTDIV
Bit 5
Basic Timer1 clock divide. This bit together with the BTSSEL bit, selects
the clock source for BTCNT2.
BTSSEL
BTDIV
BTCNT2 Clock Source
0
0
ACLK
0
1
ACLK/256
1
0
SMCLK
1
1
ACLK/256
BTFRFQx
Bits
4−3
f
LCD
frequency. These bits control the LCD update frequency.
00
f
ACLK
/32
01
f
ACLK
/64
10
f
ACLK
/128
11
f
ACLK
/256
BTIPx
Bits
2−0
Basic Timer1 Interrupt Interval.
000 f
CLK2
/2
001 f
CLK2
/4
010 f
CLK2
/8
011 f
CLK2
/16
100 f
CLK2
/32
101 f
CLK2
/64
110 f
CLK2
/128
111
f
CLK2
/256
Summary of Contents for MSP430x4xx Family
Page 1: ...MSP430x4xx Family 2007 Mixed Signal Products User s Guide SLAU056G ...
Page 2: ......
Page 6: ...vi ...
Page 114: ...3 76 RISC 16 Bit CPU ...
Page 304: ...5 20 FLL Clock Module ...
Page 340: ...7 8 Supply Voltage Supervisor ...
Page 348: ...8 8 16 Bit Hardware Multiplier ...
Page 372: ...9 24 32 Bit Hardware Multiplier ...
Page 400: ...10 28 DMA Controller ...
Page 428: ...13 10 Basic Timer1 ...
Page 466: ...15 24 Timer_A ...
Page 522: ...17 30 USART Peripheral Interface UART Mode ...
Page 544: ...18 22 USART Peripheral Interface SPI Mode ...
Page 672: ...23 12 Comparator_A ...
Page 692: ...24 20 LCD Controller ...
Page 746: ...26 28 ADC12 ...