Texas Instruments MSP430x4xx Family, User Manual

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DMA Operation
10-18 DMA Controller
10.2.9 Using the USCI_B I
2
C Module with the DMA Controller
The USCI_B I
2
C module provides two trigger sources for the DMA controller.
The USCI_B I
2
C module can trigger a transfer when new I
2
C data is received
and when data is needed for transmit.
A transfer is triggered if UCB0RXIFG is set. The UCB0RXIFG is cleared
automatically when the DMA controller acknowledges the transfer. If
UCB0RXIE is set, UCB0RXIFG will not trigger a transfer.
A transfer is triggered if UCB0TXIFG is set. The UCB0TXIFG is cleared
automatically when the DMA controller acknowledges the transfer. If
UCB0TXIE is set, UCB0TXIFG will not trigger a transfer.
10.2.10 Using ADC12 with the DMA Controller
MSP430 devices with an integrated DMA controller can automatically move
data from any ADC12MEMx register to another location. DMA transfers are
done without CPU intervention and independently of any low-power modes.
The DMA controller increases throughput of the ADC12 module, and
enhances low-power applications allowing the CPU to remain off while data
transfers occur.
DMA transfers can be triggered from any ADC12IFGx flag. When CONSEQx
= {0,2} the ADC12IFGx flag for the ADC12MEMx used for the conversion can
trigger a DMA transfer. When CONSEQx = {1,3}, the ADC12IFGx flag for the
last ADC12MEMx in the sequence can trigger a DMA transfer. Any
ADC12IFGx flag is automatically cleared when the DMA controller accesses
the corresponding ADC12MEMx.
10.2.11 Using DAC12 With the DMA Controller
MSP430 devices with an integrated DMA controller can automatically move
data to the DAC12_xDAT register. DMA transfers are done without CPU
intervention and independently of any low-power modes. The DMA controller
increases throughput to the DAC12 module, and enhances low-power
applications allowing the CPU to remain off while data transfers occur.
Applications requiring periodic waveform generation can benefit from using
the DMA controller with the DAC12. For example, an application that produces
a sinusoidal waveform may store the sinusoid values in a table. The DMA
controller can continuously and automatically transfer the values to the
DAC12 at specific intervals creating the sinusoid with zero CPU execution.
The DAC12_xCTL DAC12IFG flag is automatically cleared when the DMA
controller accesses the DAC12_xDAT register.
10.2.12 Writing to Flash With the DMA Controller
MSP430 devices with an integrated DMA controller can automatically move
data to the Flash memory. DMA transfers are done without CPU intervention
and independent of any low-power modes. The DMA controller performs the
move of the data word/byte to the Flash. The write timing control is done by
the Flash controller. Write transfers to the Flash memory succeed if the Flash
controller set−up is prior to the DMA transfer and if the Flash is not busy.